Double-flash switching device and server

A server, wherein the server comprises a double-Flash switching device

• comprising:
• a target chip;
• a first Flash chip and a second Flash chip, wherein the first Flash chip and the second Flash chip are individually burnt with a firmware of the target chip, and are connected to the target chip by using a bus;
• a jumper cap, wherein the jumper cap has a first pin, a second pin and a third pin, the first pin is connected to an enabling pin of the first Flash chip, the second pin is connected to ground, and the third pin is connected to an enabling pin of the second Flash chip;
• and
• an insulated-gate-type field-effect transistor, wherein two different electrodes of the insulated-gate-type field-effect transistor are connected to the first pin and the third pin, and the insulated-gate-type field-effect transistor is configured to be switched on or switched off to cause the two different electrodes to have different electrical levels;
• and the target chip is configured to, based on connection states of the first pin, the second pin and the third pin of the jumper cap, load the firmware from the first Flash chip or the second Flash chip;
• the insulated-gate-type field-effect transistor is an N-channel metal-oxide-semiconductor (NMOS) transistor;
• a drain electrode of the NMOS transistor is connected to a power supply by a first resistor, a gate electrode of the NMOS transistor is connected to the power supply by a second resistor, and a source electrode of the NMOS transistor is connected to the ground;
• and
• the first pin is connected to the drain electrode of the NMOS transistor, and the third pin is connected to the gate electrode of the NMOS transistor.

A chassis, wherein the chassis comprises a double-Flash switching device

• comprising:
• a target chip;
• a first Flash chip and a second Flash chip, wherein the first Flash chip and the second Flash chip are individually burnt with a firmware of the target chip, and are connected to the target chip by using a bus;
• a jumper cap, wherein the jumper cap has a first pin, a second pin and a third pin, the first pin is connected to an enabling pin of the first Flash chip, the second pin is connected to ground, and the third pin is connected to an enabling pin of the second Flash chip;
• and
• an insulated-gate-type field-effect transistor, wherein two different electrodes of the insulated-gate-type field-effect transistor are connected to the first pin and the third pin, and the insulated-gate-type field-effect transistor is configured to be switched on or switched off to cause the two different electrodes to have different electrical levels;
• and the target chip is configured to, based on connection states of the first pin, the second pin and the third pin of the jumper cap, load the firmware from the first Flash chip or the second Flash chip;
• the insulated-gate-type field-effect transistor is an N-channel metal-oxide-semiconductor (NMOS) transistor;
• a drain electrode of the NMOS transistor is connected to a power supply by a first resistor, a gate electrode of the NMOS transistor is connected to the power supply by a second resistor, and a source electrode of the NMOS transistor is connected to the ground;
• and
• the first pin is connected to the drain electrode of the NMOS transistor, and the third pin is connected to the gate electrode of the NMOS transistor.