Neural network hardware acceleration via sequentially connected computation modules

An integrated circuit comprising:

• a memory configured to store values and to transmit stored values;
• and
• a plurality of sequentially connected computation modules, each computation module among the plurality of sequentially connected computation modules including:
• a processor including circuitry configured to
• receive an input data value and a weight value from the memory,
• perform a mathematical operation on the input data value and the weight value to produce a resultant data value,
• wherein the processor is connected to the memory through a memory interconnect, and
• an adder including circuitry configured to
• receive the resultant data value directly from the processor,
• receive one of a preceding resultant data value and a preceding sum value directly from a preceding adder of a preceding computation module among the plurality of sequentially connected computation modules,
• add the resultant data value to the one of the preceding resultant data value and the preceding sum value to produce a sum value, and
• transmit one of the resultant data value and the sum value to the memory or directly to a subsequent adder of a subsequent computation module among the plurality of sequentially connected computation modules,
• wherein the adder is directly connected to the processor, the preceding adder, and the subsequent adder, and is connected to the memory through the memory interconnect;
• a sequencer including circuitry configured to cause the processor and adder to transmit, receive, and perform operations according to a program including instructions to perform neural network inference;
• and
• a controller including circuitry further configured to, in accordance with the program,
• cause, in a first time step, a first computation module to request a first input data value from a first memory bank among the plurality of memory banks of the memory,
• cause, in a second time step immediately subsequent to the first time step,
• the first memory bank to transmit the first input data value to the first computation module, and
• a second computation module to request a second input data value from a second memory bank among the plurality of memory banks of the memory,
• cause, in a third time step immediately subsequent to the second time step,
• the first computation module to perform a mathematical operation on the first input data value to produce a first resultant data value,
• the first computation module to transmit the first resultant data value to the second computation module, and
• the second memory bank to transmit the second input data value to the second computation module, and
• cause, in a fourth time step immediately subsequent to the third time step,
• the second computation module to perform a mathematical operation on the second input data value to produce a second resultant data value,
• the second computation module to add the first resultant data value to the second resultant data value to produce a first sum value, and
• the second computation module to transmit the first sum value to the memory, and
• cause, in a fifth time step immediately subsequent to the fourth time step,
• the memory to store the first sum value received from the second computation module in a fourth memory bank among the plurality of memory banks of the memory.

A portion of integrated circuitry comprising:

• a first input data path connectable to a memory,
• a processor directly connected to the first input data path, the processor including circuitry configured to perform a convolution operation,
• a second input data path directly connectable to a preceding adder,
• an adder directly connected to the processor and the second input data path, the adder including circuitry configured to add,
• a first output data path directly connected to the adder and connectable to the memory,
• a second output data path directly connected to the adder and directly connectable to a subsequent adder,
• a first bidirectional control path directly connectable to a preceding sequencer,
• a sequencer directly connected to the first bidirectional control path, the sequencer including circuitry configured to transmit signals to the processor and adder according to a program, and
• a second bidirectional control path directly connectable to a subsequent sequencer,
• a third input data path connectable to the memory,
• a fourth input data path directly connectable to a preceding line register,
• a line register directly connected to the third input data path and the fourth input data path, and
• a third output data path directly connected to the line register and connectable to a subsequent line register.