Compute-in-memory cell

A device, comprising:

• a select circuit configured to receive read select signals and an input signal and provide read word line output signals on a first read word line and a second read word line based on the read select signals and the input signal;
• a memory circuit including:
• a first memory cell configured to store a first bit at a first node;
• and
• a second memory cell configured to store a second bit at a second node;
• and
• a multiply circuit configured to receive the read word line output signals, the first bit, and the second bit and provide a multiplication result,
• the multiply circuit configured to perform logic functions of:
• a first logic element configured to perform an OR function and including a first node input terminal connected to the first node, a first read word line input terminal connected to the first read word line, and a first output terminal;
• a second logic element configured to perform an OR function and including a second mode input terminal connected to the second node, a second read word line input terminal connected to the second read word line, and a second output terminal;
• and
• a third logic element configured to perform a NAND function and including a first input terminal connected to the first output terminal of the first logic element and a second input terminal connected to the second output terminal of the second logic element, wherein the first input terminal and the second input terminal are different nodes.

A method of multiplying in an integrated circuit memory, comprising:

• storing a first bit at a first node in a first memory cell;
• storing a second bit at a second node in a second memory cell;
• receiving read select signals and an input signal at a select circuit;
• outputting, by the select circuit, read word line output signals based on the read select signals and the input signal;
• receiving the read word line output signals, the first bit, and the second bit at a multiply circuit;
• and
• outputting, by the multiply circuit, a multiplication result
• wherein receiving the read word line output signals, the first bit, and the second bit at a multiply circuit includes:
• receiving one of the read word line output signals and the first bit at a first logic element configured to perform an OR function and including a first output terminal:
• receiving another one of the read word line output signals and the second bit at a second logic element configured to perform an OR function and including a second output terminal:
• receiving a first output from the first output terminal of the first logic element at a first input terminal of a third logic element configured to perform a NAND function;
• and
• receiving a second output from the second output terminal of the second logic element at a second input terminal of the third logic element, wherein the first input terminal and the second input terminal are different nodes.