Circuit and method for floating-point addition

A method comprising:

• computing exponent differences between exponents of a plurality of floating-point (FP) inputs;
• generating a plurality of aligned FP addends by aligning the plurality of FP inputs based on the exponent differences computed, the plurality of aligned FP addends at a higher FP precision relative to a lower FP precision of the plurality of FP inputs, the aligning including shifting of at least one FP input of the plurality of FP inputs, the shifting avoiding use of a sticky bit, the sticky bit otherwise used in recording shifting of the at least one FP input beyond the higher FP precision;
• generating a higher precision FP sum at the higher FP precision by summing the plurality of aligned FP addends, simultaneously;
• transforming the higher precision FP sum at the higher FP precision into a lower precision FP sum at the lower FP precision;
• and
• outputting the lower precision FP sum.

A hardware device comprising:

• at least one memory;
• and
• a circuit including an exponent comparison stage, an alignment stage, a summation stage, and a transformation stage,
• the exponent comparison stage configured to compute exponent differences between exponents of a plurality of floating-point (FP) inputs,
• the alignment stage configured to generate a plurality of aligned FP addends by aligning the plurality of FP inputs based on the exponent differences computed, the plurality of aligned FP addends at a higher FP precision relative to a lower FP precision of the plurality of FP inputs, the aligning including shifting of at least one FP input of the plurality of FP inputs, the shifting avoiding use of a sticky bit, the sticky bit otherwise used in recording shifting of the at least one FP input beyond the higher FP precision,
• the summation stage configured to generate a higher precision FP sum at the higher FP precision by summing the plurality of aligned FP addends, simultaneously, and
• the transformation stage configured to transform the higher precision FP sum, at the higher FP precision, into a lower precision FP sum, at the lower FP precision, and output the lower precision FP sum to the at least one memory or at least one other circuit of the hardware device, the at least one other circuit configured to employ the lower precision FP sum to advance computation performed by the hardware device.

An apparatus comprising:

• means for computing exponent differences between exponents of a plurality of floating-point (FP) inputs;
• means for generating a plurality of aligned FP addends by aligning the plurality of FP inputs based on the exponent differences computed, the plurality of aligned FP addends at a higher FP precision relative to a lower FP precision of the plurality of FP inputs, the aligning including shifting of at least one FP input of the plurality of FP inputs, the shifting avoiding use of a sticky bit, the sticky bit otherwise used in recording shifting of the at least one FP input beyond the higher FP precision;
• means for generating a higher precision FP sum at the higher FP precision by summing the plurality of aligned FP addends, simultaneously;
• means for transforming the higher precision FP sum at the higher FP precision into a lower precision FP sum at the lower FP precision;
• and
• means for outputting the lower precision FP sum.