Energy efficiency using a power saving clock buffer for clock grid-based scanning

A processor comprising:

• one or more data latches configured for functional data latching and scan data latching;
• and
• a local clock buffer configured to provide a functional clock signal and a scan clock signal to the one or more data latches, the local clock buffer comprising:
• a grid node that receives a global clock signal from a global clock grid;
• a clock enable latch configured to latch a clock enable signal, wherein the clock enable latch is clocked based on the global clock signal;
• a clock gate configured to output the functional clock signal in dependence upon a latched value of the clock enable signal;
• a scan clock enable latch configured to latch a scan enable signal, wherein the scan clock enable latch is a non-clocked latch;
• and
• a scan clock gate coupled to an output of the clock gate and configured to output the scan clock signal in dependence upon a latched value of the scan enable signal.

A method of improving energy efficiency using a power saving clock buffer for clock grid-based scanning, the method comprising:

• generating, by a local clock buffer, a functional clock signal;
• latching, in a non-clocked latch of the local clock buffer, a scan enable signal;
• disabling, based on the scan enable signal, an output of the functional clock signal;
• deriving, by a scan clock gate of the local clock buffer, a scan clock signal from the functional clock signal;
• and
• outputting the scan clock signal.