Autonomous memory power collapse

Abstract

Power control in a computing device may include timing a periodic time interval associated with intervals of memory accesses by a first processor alternating with intervals of inactivity of the first processor, and powering down memory controller circuitry during the intervals of first processor inactivity while maintaining power supplied to a system-level cache. Maintaining the power supplied to the system-level cache may allow a second processor to continue accessing the system-level cache even while the memory controller circuitry is powered down. Power may be restored to the memory controller circuitry during the intervals of memory access by the first processor.

Dependencies are inferred from the claim text.