Interrupt handling method and apparatus for slow peripherals
AssigneeTexas Instruments Incorporated
InventorsManeesh Soni, Rajeev Suvarna, Nikunj Khare
Life of this patent
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Abstract
Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
Claims21
A circuit, comprising:
- a first flip-flop including a first input and an output, wherein the first flip-flop is configured to:
- receive, at the first input, a first signal representing an interrupt request;
- and
- generate, at the output, a first output signal based on the first signal;
- a second flip-flop including a first input and an output, wherein the second flip-flop is configured to:
- receive, at the first input, a second signal representing an acknowledgement of the interrupt request;
- and
- generate, at the output, a second output signal based on the second signal;
- and
- a third flip-flop including a first input, a second input, and an output, the first input coupled to the output of the first flip-flop, and the second input coupled to the output of the second flip-flop, wherein the third flip-flop is configured to:
- generate, at the output, a third output signal based on the first output signal and the second output signal.
A method, comprising:
- receiving, at a first input of a first flip-flop, a first signal representing an interrupt request, wherein the first flip-flop includes the first input and an output;
- generating, at the output of the first flip-flop, a first output signal based on the first signal;
- receiving, at a first input of a second flip-flop, a second signal representing an acknowledgement of the interrupt request, wherein the second flip-flop includes the first input and an output;
- generating, at the output of the second flip-flop, a second output signal based on the second signal;
- and
- generating, at an output of a third flip-flop, a third output signal based on the first output signal and the second output signal, wherein the third flip-flop includes a first input, a second input, and the output, and wherein the first input is coupled to the output of the first flip-flop, and the second input is coupled to the output of the second flip-flop.
A system comprising:
- a first circuit configured to:
- operate based on a first clock signal;
- and
- produce an acknowledgement signal the acknowledgment signal synchronized to the first clock;
- a second circuit configured to:
- operate based on a second clock signal, wherein the second clock signal is slower than the first clock signal;
- and
- produce an interrupt request signal;
- and
- a third circuit coupled between the first circuit and the second circuit, the third circuit comprising:
- a first flip-flop configured to generate a synchronized interrupt request signal synchronized to the second clock signal;
- a second flip-flop configured to receive the synchronized interrupt request signal and to provide an interrupt input signal based on the synchronized interrupt request signal;
- and
- an interrupt clear circuit configured to:
- receive the acknowledgment signal from the first circuit;
- and
- provide, to the second flip-flop, a clear signal that asynchronously resets the second flip-flop with respect to the second clock signal in response to the acknowledgment signal.
Dependencies are inferred from the claim text.