Power savings by register insertion in large combinational circuits

A method comprising:

• receiving a first clock signal via a main register, wherein the main register is configurable to receive an output of programmable logic circuitry;
• receiving a first pulse of a second clock signal via a first register that splits the programmable logic circuitry into a first portion and a second portion, wherein the second portion consumes less dynamic power prior to the first register receiving the first pulse than the second portion would consume without the first register preceding it in a signal propagation path;
• and
• receiving a second pulse of the second clock signal via a second register in the signal propagation path.

One or more tangible, non-transitory, computer-readable media, comprising instructions that cause processing circuitry to generate a bitstream to:

• configure a main register of a programmable logic device to receive a first clock signal via the main register, wherein the main register is configurable to receive an output of programmable logic circuitry of the programmable logic device;
• configure a first register inserted into the programmable logic circuitry to receive a pulse of a second clock signal via the first register inserted into the programmable logic circuitry, wherein the programmable logic circuitry downstream of the first register along a signal propagation path consumes less dynamic power prior to receiving the pulse than after than receiving the pulse;
• and
• configure the first register to latch an intermediate result of the programmable logic circuitry via the first register on a rising edge of the pulse.