Semiconductor test device and semiconductor test system

A semiconductor test device for testing an electrical connection of a semiconductor, comprising:

• a membrane portion including a first surface and a plurality of aperture patterns extending toward a direction of a second surface opposite to the first surface,
• wherein the membrane portion comprises:
• a metal thin-film portion including the plurality of aperture patterns;
• and
• an insulating layer portion having an insulating material coated on a surface of the metal thin-film portion,
• wherein a conductive thin-film layer is formed on a side surface of each of the plurality of aperture patterns so that adjacent aperture patterns are insulated from each other and an electrical connection path is established from a top to a bottom of each of the plurality of aperture patterns,
• wherein the semiconductor test device further comprises, on an upper portion of the membrane portion, a bump guide portion having a plurality of openings corresponding to the plurality of aperture patterns, and
• wherein the plurality of aperture patterns are formed in an active area of the membrane portion and a plurality of alignment keys are formed in a dummy area located outside the active area.

A semiconductor test system for testing an electrical connection of a semiconductor, comprising:

• a semiconductor test device;
• an interposer on which a pad configured to make contact with a lower portion of the semiconductor test device is arranged;
• a housing formed to surround the semiconductor test device and connected to the semiconductor test device via a fixing means,
• wherein the semiconductor test device includes a membrane portion including a first surface and a plurality of aperture patterns extending toward a direction of a second surface opposite to the first surface,
• wherein the membrane portion comprises:
• a metal thin-film portion including the plurality of aperture patterns;
• and
• an insulating layer portion having an insulating material coated on a surface of the metal thin-film portion,
• wherein a conductive thin-film layer is formed on a side surface of each of the plurality of aperture patterns so that adjacent aperture patterns are insulated from each other and an electrical connection path is established from a top to a bottom of each of the plurality of aperture patterns, and
• wherein the semiconductor test system further comprises a vibration means configured to apply vibration to at least one of the membrane portion, the interposer, or the housing.

A semiconductor test system for testing an electrical connection of a semiconductor, comprising:

• a semiconductor test device;
• an interposer on which a pad configured to make contact with a lower portion of the semiconductor test device is arranged;
• a housing formed to surround the semiconductor test device and connected to the semiconductor test device via a fixing means,
• wherein the semiconductor test device includes a membrane portion including a first surface and a plurality of aperture patterns extending toward a direction of a second surface opposite to the first surface,
• wherein the membrane portion comprises:
• a metal thin-film portion including the plurality of aperture patterns;
• and
• an insulating layer portion having an insulating material coated on a surface of the metal thin-film portion,
• wherein a conductive thin-film layer is formed on a side surface of each of the plurality of aperture patterns so that adjacent aperture patterns are insulated from each other and an electrical connection path is established from a top to a bottom of each of the plurality of aperture patterns,
• wherein the metal thin-film portion comprises a first metal thin-film portion and a second metal thin-film portion connected to an upper portion of the first metal thin-film portion, a width of a first aperture pattern of the first metal thin-film portion is greater than a width of a second aperture pattern of the second metal thin-film portion, and
• wherein a portion where a difference occurs between the first metal thin-film portion and the second metal thin-film portion is provided as a cantilever portion protruding toward the aperture pattern.

A semiconductor test system for testing an electrical connection of a semiconductor, comprising:

• a semiconductor test device;
• an interposer on which a pad configured to make contact with a lower portion of the semiconductor test device is arranged;
• a housing formed to surround the semiconductor test device and connected to the semiconductor test device via a fixing means,
• wherein the semiconductor test device includes a membrane portion including a first surface and a plurality of aperture patterns extending toward a direction of a second surface opposite to the first surface,
• wherein the membrane portion comprises:
• a metal thin-film portion including the plurality of aperture patterns;
• and
• an insulating layer portion having an insulating material coated on a surface of the metal thin-film portion,
• wherein a conductive thin-film layer is formed on a side surface of each of the plurality of aperture patterns so that adjacent aperture patterns are insulated from each other and an electrical connection path is established from a top to a bottom of each of the plurality of aperture patterns, and
• wherein the semiconductor test system further comprises an interface printed circuit board (PCB) electrically connected to a lower portion of the interposer and functioning as a redistribution layer (RDL) for distributing transmission paths of electrical signals.

A semiconductor test system for testing an electrical connection of a semiconductor, comprising:

• a semiconductor test device;
• an interposer on which a pad configured to make contact with a lower portion of the semiconductor test device is arranged;
• a housing formed to surround the semiconductor test device and connected to the semiconductor test device via a fixing means,
• wherein the semiconductor test device includes a membrane portion including a first surface and a plurality of aperture patterns extending toward a direction of a second surface opposite to the first surface,
• the membrane portion comprises:
• a metal thin-film portion including the plurality of aperture patterns;
• and
• an insulating layer portion having an insulating material coated on a surface of the metal thin-film portion,
• wherein a conductive thin-film layer is formed on a side surface of each of the plurality of aperture patterns so that adjacent aperture patterns are insulated from each other and an electrical connection path is established from a top to a bottom of each of the plurality of aperture patterns,
• wherein the plurality of aperture patterns are formed in an active area of the membrane portion, a plurality of alignment keys are formed in a dummy area located outside the active area, and
• wherein the plurality of alignment keys are formed at positions corresponding to alignment pins on a lower portion of the semiconductor.