Semiconductor package

A semiconductor package, comprising:

• a package substrate;
• first semiconductor chips vertically stacked on each other;
• a second semiconductor chip on a bottom surface of a lowermost first semiconductor chip of the first semiconductor chips and on a top surface of the package substrate;
• a third semiconductor chip on a top surface of an uppermost first semiconductor chip of the first semiconductor chips;
• and
• a mold layer on a bottom surface of the third semiconductor chip and enclosing the first semiconductor chips and the second semiconductor chip,
• wherein each of the first semiconductor chips comprises:
• upper pads on a top surfaces of each of the first semiconductor chips, a first connection terminal on a top surface of each of the upper pads, and lower pads on a bottom surfaces of each of the first semiconductor chips,
• wherein the second semiconductor chip comprises:
• chip pads on a top surface of the second semiconductor chip, and
• second connection terminals on a top surface of each of the chip pads, and
• wherein each of the first semiconductor chips is electrically connected to another of the first semiconductor chips or the third semiconductor chip through the first connection terminals,
• the second semiconductor chip is electrically connected to the lowermost one of the first semiconductor chips through the second connection terminals,
• each of the first and second connection terminals comprises a solder ball or a solder bump,
• a bottom surface of the second semiconductor chip is coplanar with a bottom surface of the mold layer,
• the second semiconductor chip is a bottommost chip between the package substrate and the third semiconductor chip,
• the third semiconductor chip comprises a logic chip,
• a width of the third semiconductor chip is larger than a width of each of the first semiconductor chips and larger than a width of the second semiconductor chip, and
• a thickness of the third semiconductor chip ranges from 100 μm to 200 μm.

A semiconductor package, comprising:

• a package substrate;
• a first chip structure on a top surface of the package substrate;
• a first semiconductor chip on the package substrate and horizontally spaced apart from the first chip structure;
• and
• a first mold layer on the package substrate and enclosing the first chip structure and the first semiconductor chip,
• wherein the first chip structure comprises:
• a second semiconductor chip,
• a plurality of third semiconductor chips vertically stacked on the package substrate and being between the package substrate and the second semiconductor chip, each of the third semiconductor chips comprising penetration vias penetrating therethrough and exposed to an outside from a bottom surface thereof,
• first pads on a bottom surface of a lowermost third semiconductor chip of the third semiconductor chips and directly coupled to the penetration vias of the lowermost third semiconductor chip of the third semiconductor chips, and
• a second mold layer between the package substrate and the second semiconductor chip to enclose the third semiconductor chips, and
• wherein the second semiconductor chip comprises a logic chip,
• the lowermost third semiconductor chip of the third semiconductor chips is a bottommost chip between the package substrate and the second semiconductor chip,
• a width of the second semiconductor chip is larger than a width of each of the third semiconductor chips,
• a side surface of the second semiconductor chip is vertically aligned to a side surface of the second mold layer,
• an active surface of the second semiconductor chip faces the package substrate, and
• an active surface of an uppermost third semiconductor chip of the third semiconductor chips faces the second semiconductor chip.