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US 12,740,490 B2Granted
Molded direct bonded and interconnected stack
AssigneeAdeia Semiconductor Bonding Technologies Inc.
InventorsGuilian Gao, Cyprian Emeka Uzoh, Jeremy Alfred Theil, Belgacem Haba, Rajesh Katkar
Life of this patent
Estimating the term…
Abstract
Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
Claims35
A microelectronic assembly, comprising:
- a plurality of adjacent stacks of multiple microelectronic elements, each stack comprising:
- a first substrate having a first microelectronic circuit element in the first substrate;
- a second substrate having a second microelectronic circuit element in the second substrate, the second substrate hybrid bonded to the first substrate, electrically coupling the first substrate to the second substrate without adhesive;
- and
- a first encapsulant covering at least a side edge of the second substrate facing a side edge of an adjacent stack;
- a base substrate, the plurality of stacks attached to the base substrate, the plurality of stacks laterally spaced from one another;
- and
- a second encapsulant disposed in the lateral space between the plurality of adjacent stacks.
5 more elements
A microelectronic assembly, comprising:
- a host element with a surface;
- a first stack of hybrid bonded dies attached to the surface of the host element, the first stack of hybrid bonded dies including a first die hybrid bonded to a second die without an adhesive;
- a second stack of hybrid bonded dies attached to the surface of the host element, the second stack laterally spaced from the first stack, the second stack of hybrid bonded dies including a third die hybrid bonded to a fourth die without an adhesive;
- and
- a first encapsulant disposed in the lateral space between the first stack and the second stack.
2 more elements
An interconnected stack comprising:
- a first die comprising:
- a first dielectric surface with a first plurality of conductive features embedded within and exposed at the first dielectric surface;
- a first plurality of microelectronic devices embedded within the first die and in electrical communication with the first plurality of conductive features;
- and
- an optical component located within the first die;
- a second die directly bonded to the first die, the second die comprising:
- a second dielectric surface with a second plurality of conductive features embedded within and exposed at the second dielectric surface, the second dielectric surface directly bonded to the first dielectric surface of the first die without an intervening adhesive such that the second plurality of conductive features is bonded to the first plurality of conductive features without an intervening adhesive;
- a third surface opposite the second dielectric surface;
- and
- a second plurality of microelectronic devices embedded within the second die, the second plurality of microelectronic devices in electrical connection with the second plurality of conductive features;
- and
- a top die provided on the second die, the top die comprising:
- a fourth surface provided over the third surface of the second die;
- and
- a top surface opposite the fourth surface,
- wherein at least a portion of the top surface of the top die is configured to be interconnected to the optical component located within the first die.
13 more elements
An interconnected stack comprising:
- a first die comprising:
- a first dielectric surface;
- a first plurality of microelectronic devices embedded within the first die;
- and
- an optical component located within the first die;
- a second die directly bonded to the first die, the second die comprising:
- a second plurality of microelectronic devices embedded within the second die;
- a second dielectric surface directly bonded to the first dielectric surface of the first die without an intervening adhesive such that the second plurality of microelectronic devices is in electrical communication with the first plurality of microelectronic devices;
- and
- a third surface opposite the second dielectric surface;
- and
- a top die provided on the second die, the top die comprising:
- a fourth surface provided over the third surface of the second die;
- and
- a top surface opposite the fourth surface,
- wherein at least a portion of the top surface of the top die is configured to be interconnected to the optical component located within the first die.
13 more elements
Dependencies are inferred from the claim text.