Semiconductor package

A method of manufacturing a semiconductor package, the method comprising:

• forming a first structure including a first semiconductor chip and a first filling layer covering side surfaces of the first semiconductor chip and at least a portion of a first active surface of the first semiconductor chip;
• forming a second structure on the first structure, the second structure including a second semiconductor chip on the first semiconductor chip, a second filling layer covering side surfaces of the second semiconductor chip and a first lower post electrically connected to the first semiconductor chip;
• forming a connection member including a redistribution layer electrically connected to the first lower post on the second structure;
• and
• forming a conductive pattern electrically connected to the redistribution layer on the connection member,
• wherein the first structure further includes a first bump pattern including a first bump disposed on a connection pad of the first semiconductor chip and a first dummy bump disposed on a level the same as a level of the first bump.