US 12,740,486 B2Granted

Electronic device including stacked semiconductor chips and method of manufacturing the same

AssigneeNanya Technology Corporation

InventorShing-Yih Shih

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Abstract

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.

Claims18

Dependent claims

An electronic device, comprising:

a first semiconductor chip, wherein the first semiconductor chip comprises a first lower structure, a first conductive structure disposed on the first lower structure, a first base portion disposed on the first conductive structure, a first upper structure disposed on the first base portion, and a first encapsulant disposed around the first lower structure, the first conductive structure, the first base portion, and the first upper structure to define a lateral surface of the first semiconductor chip at an outer surface of the first encapsulant;
a second semiconductor chip stacked on the first semiconductor chip, and electrically connected to the first semiconductor chip by hybrid bonding, wherein the second semiconductor chip comprises a second lower structure, a second conductive structure disposed on the second lower structure, a second base portion disposed on the second conductive structure, and a second upper structure disposed on the second base portion, wherein the second semiconductor chip has a lateral surface defined at an outer surface of the second base portion;
and
a third semiconductor chip stacked on the second semiconductor chip, and electrically connected to the second semiconductor chip through a plurality of bumps, wherein the third semiconductor chip comprises a third lower structure, a third conductive structure disposed on the third lower structure, a third base portion disposed on the third conductive structure, a third upper structure disposed on the third base portion, and a third encapsulant disposed around the third lower structure, the third conductive structure, the third base portion, and the third upper structure to define a lateral surface of the third semiconductor chip at an outer surface of the third encapsulant;
wherein the second semiconductor chip is bonded between the first semiconductor chip and the third semiconductor chip at a position that the second lower structure of the second semiconductor chip is in contact with the first upper structure of the first semiconductor chip and the second upper structure of the second semiconductor chip is coupled to the third lower structure of the third semiconductor chip via the bumps;
wherein the lateral surface of the first semiconductor chip is aligned with the lateral surface of the second semiconductor chip and is aligned with the lateral surface of the third semiconductor chip;
wherein a width of the second lower structure of the second semiconductor chip is greater than a width of the first lower structure of the first semiconductor chip;
wherein a width of the first conductive structure is equal to the width of the first lower structure while a width of the second conductive structure is equal to the width of the second lower structure;
wherein a width of the third lower structure of the third semiconductor chip is equal to the width of the first lower structure of the first semiconductor chip.

6 more elements

An electronic device, comprising:

a first assembly including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by hybrid bonding;
and
a second assembly including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip by hybrid bonding, wherein the second assembly is electrically connected to the first assembly through a plurality of bumps;
wherein the first semiconductor chip of the first assembly comprises a first base portion and a first encapsulant disposed around the first base portion;
wherein the second semiconductor chip of the first assembly comprises a second base portion;
wherein the third semiconductor chip of the second assembly comprises a third base portion and a third encapsulant disposed around the third base portion;
wherein the fourth semiconductor chip of the second assembly comprises a fourth base portion;
wherein a lateral surface of the first assembly is aligned with the lateral surface of the second assembly;
wherein an outer surface of the first encapsulant and an outer surface of the second base portion form the lateral surface of the first assembly;
wherein an outer surface of the third encapsulant and an outer surface of the fourth base portion form the lateral surface of the second assembly, such that the outer surface of the first encapsulant, the outer surface of the second base portion, the outer surface of the third encapsulant, and the outer surface of the fourth base portion are aligned with each other.

7 more elements

Dependencies are inferred from the claim text.

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Abstract

An electronic device, comprising:

a first semiconductor chip, wherein the first semiconductor chip comprises a first lower structure, a first conductive structure disposed on the first lower structure, a first base portion disposed on the first conductive structure, a first upper structure disposed on the first base portion, and a first encapsulant disposed around the first lower structure, the first conductive structure, the first base portion, and the first upper structure to define a lateral surface of the first semiconductor chip at an outer surface of the first encapsulant;
a second semiconductor chip stacked on the first semiconductor chip, and electrically connected to the first semiconductor chip by hybrid bonding, wherein the second semiconductor chip comprises a second lower structure, a second conductive structure disposed on the second lower structure, a second base portion disposed on the second conductive structure, and a second upper structure disposed on the second base portion, wherein the second semiconductor chip has a lateral surface defined at an outer surface of the second base portion;
and
a third semiconductor chip stacked on the second semiconductor chip, and electrically connected to the second semiconductor chip through a plurality of bumps, wherein the third semiconductor chip comprises a third lower structure, a third conductive structure disposed on the third lower structure, a third base portion disposed on the third conductive structure, a third upper structure disposed on the third base portion, and a third encapsulant disposed around the third lower structure, the third conductive structure, the third base portion, and the third upper structure to define a lateral surface of the third semiconductor chip at an outer surface of the third encapsulant;
wherein the second semiconductor chip is bonded between the first semiconductor chip and the third semiconductor chip at a position that the second lower structure of the second semiconductor chip is in contact with the first upper structure of the first semiconductor chip and the second upper structure of the second semiconductor chip is coupled to the third lower structure of the third semiconductor chip via the bumps;
wherein the lateral surface of the first semiconductor chip is aligned with the lateral surface of the second semiconductor chip and is aligned with the lateral surface of the third semiconductor chip;
wherein a width of the second lower structure of the second semiconductor chip is greater than a width of the first lower structure of the first semiconductor chip;
wherein a width of the first conductive structure is equal to the width of the first lower structure while a width of the second conductive structure is equal to the width of the second lower structure;
wherein a width of the third lower structure of the third semiconductor chip is equal to the width of the first lower structure of the first semiconductor chip.

6 more elements