Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip including a first substrate having a first surface and a second surface opposite to the first surface, a plurality of through electrodes that penetrate the first substrate, first bonding pads on the first surface of the first substrate and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first surface of the first substrate, and a first passivation layer on the first surface of the first substrate and that exposes at least portions of the first bonding pads and the first test pad;
• and
• a second semiconductor chip on the first surface of the first semiconductor chip, the second semiconductor chip including a second substrate having a third surface and a fourth surface opposite to the third surface, third bonding pads on the third surface of the second substrate, a second test pad on the third surface of the second substrate, and a second passivation layer on the third surface of the second substrate and that exposes at least portions of the third bonding pads and the second test pad,
• wherein at least one first bonding pad of the first bonding pads and the first test pad are disposed adjacent to each other in the first passivation layer;
• wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other,
• wherein the first passivation layer and the second passivation layer are directly bonded to each other, and
• wherein the first and second test pads have a first diameter, and the first and third bonding pads have a second diameter that is smaller than the first diameter.

A semiconductor package, comprising:

• a package substrate;
• a first semiconductor chip including a first substrate having a first surface and a second surface opposite to the first surface, a plurality of through electrodes that penetrate the first substrate, first bonding pads on the first surface of the first substrate and electrically connected to respective ones of the plurality of through electrodes, second bonding pads on the second surface and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first surface of the first substrate, and a first passivation layer on the first surface of the first substrate and that exposes at least portions of the first bonding pads and the first test pad, wherein the first semiconductor chip is on the package substrate with conductive bumps therebetween that are on the second bonding pads;
• and
• a second semiconductor chip including a second substrate having a third surface and a fourth surface opposite to the third surface, third bonding pads on the third surface of the second substrate, a second test pad on the third surface of the second substrate and a second passivation layer on the third surface of the second substrate and that exposes at least portions of the third bonding pads and the second test pad, wherein the second semiconductor chip is on the first semiconductor chip such that the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip,
• wherein at least one first bonding pad of the first bonding pads and the first test pad are disposed adjacent to each other in the first passivation layer;
• wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other, and
• wherein the first passivation layer and the second passivation layer are directly bonded to each other.