Semiconductor package

A semiconductor package comprising:

• a substrate;
• an interposer on the substrate;
• a first buffer chip on the interposer;
• a second buffer chip on the interposer, wherein the second buffer chip is spaced apart from the first buffer chip;
• a first chip stack on the substrate, wherein the first chip stack is adjacent to a first side of the interposer and directly, electrically connected to the first buffer chip by a first conductive wire;
• a second chip stack on the substrate, wherein the second chip stack is adjacent to a second side of the interposer and directly, electrically connected to the second buffer chip by a second conductive wire;
• and
• a third chip stack on the substrate, wherein the third chip stack is adjacent to a third side of the interposer and electrically connected to the interposer, the first buffer chip, and the second buffer chip by a plurality of third conductive wires.

A semiconductor package comprising:

• a substrate that includes a wiring circuit;
• an interposer on the substrate, wherein the interposer includes an interconnect circuit that is electrically connected to the wiring circuit;
• a first buffer chip on the interposer;
• a second buffer chip on the interposer, wherein the second buffer chip is spaced apart from the first buffer chip;
• and
• chip stacks on the substrate, wherein the chip stacks are horizontally adjacent to the interposer,
• wherein each of the chip stacks includes a plurality of semiconductor chips stacked vertically,
• a first subset of chip stacks, among the chip stacks is directly, electrically connected to the first buffer chip and/or the second buffer chip, and
• a second subset of chip stacks, among the chip stacks is electrically connected to the first buffer chip and/or the second buffer chip via the interconnect circuit.