System on chip having three-dimensional chiplet structure and electronic device including the system on chip
AssigneeSamsung Electronics Co., Ltd.
InventorsDaehan Youn, Kyoungmin Lee, Junho Huh, Heeseok Lee
Life of this patent
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Abstract
Provided are a system on chip (SoC) having a three-dimensional (3D) chiplet structure, and an electronic device including the SoC. The electronic device includes a printed circuit board, the SoC on the printed circuit board, and a memory device on the SoC, wherein the SoC includes an SoC package substrate, a first die arranged on the SoC package substrate, and having a logic circuit thereon, and a second die arranged on the first die, and having a logic circuit thereon.
Claims19
An electronic device comprising:
- a printed circuit board;
- a system on chip (SoC) on the printed circuit board;
- and
- a memory device on the SoC;
- an interconnection via;
- and
- an interposer substrate between the SoC and the memory device, electrically connecting the SoC to the memory device,
- wherein the SoC comprises
- a SoC package substrate;
- a first die on the SoC package substrate, and having a logic circuit thereon;
- and
- a second die on the first die, and having a logic circuit thereon,
- wherein the interconnection via vertically extends in a direction from a contact location with the first die within the SoC to an external surface of the SoC facing the memory device penetrating the interposer substrate, the contact location being outside an outermost perimeter of the second die.
An electronic device comprising:
- a printed circuit board;
- a system on chip (SoC) on the printed circuit board, and comprising at least two logic die having a logic circuit thereon;
- a memory device on the SoC;
- an interposer substrate between the SoC and the memory device, and electrically connecting the SOC to the memory device;
- and
- an interconnection via vertically extending in a direction from a contact location with one of the at least two logic die within the SoC to an external surface of the SoC facing the memory device to electrically connect the one of the at least two logic die to the memory device, penetrating the interposer substrate, the contact location being outside an outermost perimeter of another one of the at least two logic die.
A system on chip (SoC) having a three-dimensional (3D) chiplet structure, the SoC comprising:
- an SoC package substrate;
- a first die on the SoC package substrate using a first bump, and having a first logic circuit thereon;
- a second die on the first die, and having a second logic circuit thereon;
- and
- an interconnection via;
- and
- interposer substrate on an external surface of the SoC, and electrically connected to the SoC,
- wherein the first logic circuit and the second logic circuit receive an output voltage via an output voltage path, from a voltage regulator on the SoC package substrate,
- a plurality of function blocks are on at least one of the first die and the second die, and
- the interconnection via vertically extends in a direction from a contact location with the first die within the SoC to the external surface of the SoC opposite the SoC package substrate, penetrating the interposer substrate, the contact location being outside an outermost perimeter of the second die.
Dependencies are inferred from the claim text.