Chip packaging method and chip packaging structure

A chip packaging method, comprising:

• providing an encapsulated grain and a packaging substrate, the encapsulated grain comprising a plurality of first hybrid bonding structures, a plurality of third hybrid bonding structures arranged inside the encapsulated grain, and at least one chip;
• wherein the packaging substrate is a ceramic substrate and comprises a front side and a back side opposite to each other;
• a plurality of second hybrid bonding structures are formed on the front side of the packaging substrate and a plurality of connection pins are formed on the back side of the packing substrate;
• the plurality of second hybrid bonding structures are electrically connected to the plurality of connection pins through a plurality of metal posts penetrating the packaging substrate;
• and
• bonding together the plurality of first hybrid bonding structures of the encapsulated grain with the plurality of second hybrid bonding structures of the packaging substrate by medium-to-medium and metal-to-metal aligned bonding such that the encapsulated grain is bonded to the packaging substrate;
• the encapsulated grain further comprises a wafer;
• the at least one chip is bonded to the wafer, and a side of the wafer away from the at least one chip is formed with the plurality of first hybrid bonding structures;
• the plurality of third hybrid bonding structures are formed on a side of the wafer bonded to the at least one chip;
• the wafer comprises a first semiconductor substrate, and a first dielectric layer and a second dielectric layer laminated on opposite sides of the first semiconductor substrate;
• the plurality of first hybrid bonding structures are formed in the second dielectric layer;
• the plurality of third hybrid bonding structures are formed on a side surface of the first dielectric layer away from the first semiconductor substrate;
• the plurality of third hybrid bonding structures are bonded to the at least one chip;
• and a pitch of any adjacent two of the plurality of first hybrid bonding structures bonding the wafer to the packaging substrate is greater than a pitch of any adjacent two of the plurality of third hybrid bonding structures bonding the wafer to the at least one chip.