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US 12,740,433 B2Granted
Semiconductor integrated circuit, semiconductor device and method for aligning semiconductor integrated circuits
AssigneeMacronix International Co., Ltd.
InventorChin-Cheng Yang
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit, a semiconductor device and a method for aligning semiconductor integrated circuits are provided. The semiconductor integrated circuit includes a substrate and an overlay mark structure in the substrate. The overlay mark structure includes first overlay marks and second overlay marks separated from each other. A first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks.
Claims9
A semiconductor integrated circuit, comprising:
- a substrate;
- and
- an overlay mark structure in the substrate and comprising first overlay marks and second overlay marks separated from each other,
- wherein a first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks,
- wherein the overlay mark structure further comprises third overlay marks separated from each other, a third mark width of the third overlay marks is smaller than the second mark width of the second overlay marks,
- the first overlay marks are arranged along a first direction, the second overlay marks are arranged along the first direction, the third overlay marks are arranged along the first direction,
- the second overlay marks are between the first overlay marks and the third overlay marks.
4 more elements
A semiconductor integrated circuit, comprising:
- a substrate;
- and
- an overlay mark structure in the substrate and comprising first overlay marks and second overlay marks separated from each other,
- wherein a first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks,
- the overlay mark structure further comprises fifth overlay marks separated from each other, the first mark width of the first overlay marks is smaller than a fifth mark width of the fifth overlay marks,
- the first overlay marks are arranged along a first direction, the second overlay marks are arranged along the first direction, the fifth overlay marks are arranged along the first direction,
- the first overlay marks are between the second overlay marks and the fifth overlay marks.
4 more elements
A semiconductor device, comprising:
- a first semiconductor wafer comprising a first overlay mark structure, wherein the first overlay mark structure comprises a first overlay mark and a second overlay mark separated from each other, a first mark width of the first overlay mark is smaller than a second mark width of the second overlay mark;
- and
- a second semiconductor wafer bonded to the first semiconductor wafer along a first direction and comprising a second overlay mark structure, wherein the second overlay mark structure comprises a third overlay mark, the third overlay mark at least partially overlaps the first overlay mark of the first semiconductor wafer along the first direction.
Dependencies are inferred from the claim text.