Memory device, memory integrated circuit and manufacturing method thereof

A memory integrated circuit, comprising:

• memory cells, each comprising a resistive memory and a switch connected to a terminal of the resistive memory, wherein the resistive memory in each memory cell comprises:
• a top electrode;
• a composite bottom electrode, overlapped with the top electrode, and comprising a first bottom electrode and a second bottom electrode stacked on top of the first bottom electrode;
• and
• a resistance variable layer, extending between the top electrode and the composite electrode,
• wherein central regions of the top electrode, the composite bottom electrode and the resistance variable layer are vertically recessed with respect to peripheral regions of the top electrode, the composite bottom electrode and the resistance variable layer, and the peripheral region of the second bottom electrode is laterally recessed with respect to the peripheral regions of the resistance variable layer and the first bottom electrode.

A method for manufacturing a memory device, comprising:

• sequentially stacking a first bottom electrode, a second bottom electrode, a resistance variable layer and a top electrode on a substrate, wherein a passivation layer with an opening is formed on the substrate, and the first bottom electrode, the second bottom electrode, the resistance variable layer and the top electrode are recessed into the opening;
• etching through portions of the top electrode, the resistance variable layer, the second bottom electrode and the first bottom electrode outside the opening;
• and
• selectively trimming the second bottom electrode, such that the resulted second bottom electrode is laterally recessed with respect to the first bottom electrode and the resistance variable layer.