Semiconductor device

A semiconductor device that is a facedown mountable, chip-size-package type semiconductor device, the semiconductor device comprising:

• a semiconductor layer that includes a semiconductor substrate;
• a first vertical metal-oxide semiconductor (MOS) transistor an entirety of which is provided in a first region of the semiconductor layer, on a top face side of the semiconductor layer;
• a second vertical MOS transistor an entirety of which is provided in a second region adjacent to the first region in a plan view of the semiconductor layer;
• and
• a metal layer that is connected to and in contact with the semiconductor substrate, on a bottom face side of the semiconductor layer,
• wherein the semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor,
• in the plan view, the semiconductor layer is in a square shape,
• in the plan view, the first region and the second region are arranged in a first direction,
• in the plan view, a border line between the first region and the second region is a straight line that is orthogonal to the first direction, divides an area of the semiconductor layer in half, and passes through a center of the semiconductor layer,
• in the plan view, the first region includes only one first source pad and only one first gate pad, the one first source pad being connected to a first source electrode of the first vertical MOS transistor, the one first gate pad being connected to a first gate electrode of the first vertical MOS transistor,
• the first vertical MOS transistor includes:
• a first gate resistance element that is connected to the first gate electrode;
• a first gate electrode region that is, in the plan view, a region having a largest area among rectangular regions formable within the first region while encompassing the one first gate pad and excluding both the first source electrode and the first gate resistance element;
• and
• a first resistance element region that is, in the plan view, a region having a largest area among rectangular regions formable within the first region while encompassing the first gate resistance element and excluding both the first source electrode and the first gate electrode region,
• in the plan view, an entire length of an outer peripheral side among outer peripheral sides of the first gate electrode region and an entire length of an outer peripheral side among outer peripheral sides of the first resistance element region match a portion of an outer peripheral side among outer peripheral sides of the semiconductor layer, the outer peripheral side among the outer peripheral sides of the semiconductor layer being orthogonal to the border line and having a shortest distance to the one first gate pad, and
• in the plan view, the outer peripheral sides of the first resistance element region include only one corner portion among four corner portions of an outer periphery of the first gate electrode region, the one corner portion having a shortest distance to the border line and a shortest distance to one of outer peripheral sides among the outer peripheral sides of the semiconductor layer, the outer peripheral sides among the outer peripheral sides of the semiconductor layer being orthogonal to the border line.