Back-end-of-line CMOS inverter with vertical channels and methods of forming the same

A method of forming an inverter circuit, comprising:

• forming a first interlayer dielectric layer over a substrate;
• forming an etch-stop layer over the first interlayer dielectric layer;
• forming an electrically insulating structure having a slab geometry over the first interlayer dielectric layer, the electrically insulating structure comprising a first surface and a second surface that are parallel to one another and that are each oriented in respective planes that are perpendicular to a thickness direction, wherein the etch stop layer covers a top portion of the electrically insulating structure;
• forming a p-type semiconductor layer on the first surface of the electrically insulating structure;
• forming an n-type semiconductor layer on the second surface of the electrically insulating structure;
• forming a gate dielectric layer in contact with the p-type semiconductor layer and the n-type semiconductor layer;
• and
• forming a gate electrode in contact with the gate dielectric layer, wherein the etch-stop layer is positioned between the n-type semiconductor layer and the p-type semiconductor layer.

A method of fabricating a semiconductor device, comprising:

• providing a substrate having one or more lower-level metal interconnect structures;
• depositing a first interlayer dielectric material layer over the substrate;
• forming an etch-stop layer on the first interlayer dielectric material;
• patterning the first interlayer dielectric material layer to form an electrically insulating structure having a slab geometry with a first surface and a second surface that are parallel to one another, wherein the etch-stop layer covers a top portion of the electrically insulating structure;
• depositing a p-type metal-oxide semiconductor layer on the first surface;
• depositing an n-type metal-oxide semiconductor layer on the second surface;
• depositing a gate dielectric layer over the p-type metal-oxide semiconductor layer and the n-type metal-oxide semiconductor layer;
• depositing a gate electrode over the gate dielectric layer, wherein the gate electrode is in contact with the gate dielectric layer;
• forming a first source electrode and a first drain electrode in contact with the p-type metal-oxide semiconductor layer;
• and
• forming a second source electrode and a second drain electrode in contact with the n-type metal-oxide semiconductor layer, wherein the etch-stop layer is positioned between the n-type metal-oxide semiconductor layer and the p-type metal-oxide semiconductor layer.