Logic circuit and semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei Yamazaki, Jun Koyama, Masashi Tsubuku, Kosei Noda
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Abstract
To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
Claims9
A semiconductor device comprising:
- a first transistor comprising an oxide semiconductor layer including a channel formation region comprising a crystal,
- wherein an off current is 1×10−17 A or less per micrometer in channel width in the first transistor when a source-drain voltage is 1V.
A semiconductor device comprising:
- a first transistor comprising an oxide semiconductor layer including a channel formation region comprising a crystal,
- wherein an off current is 1×10−16 A or less per micrometer in channel width in the first transistor when a substrate on which the first transistor is located is 120° C.
A semiconductor device comprising:
- a first transistor, a second transistor, and a capacitor;
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
- wherein one electrode of the capacitor is electrically connected to the gate of the second transistor,
- wherein the first transistor comprises an oxide semiconductor layer including a channel formation region comprising a crystal, and
- wherein an off current is 1×10−17 A or less per micrometer in channel width in the first transistor when a source-drain voltage is 1V.
Dependencies are inferred from the claim text.