Integration of stacked logic device with passive device

A method of forming a semiconductor structure comprising:

• forming a first, a second, a third, and a fourth stack of nanosheets on a substrate, wherein the first, the second, the third, and the fourth stack of nanosheets each includes a first set of nanosheets and a second set of nanosheets on top of the first set of nanosheets and are separated by a first, a second, and a third recess respectively;
• the first stack of nanosheets and the first recess are in a passive device region;
• the second recess, the third stack of nanosheets, the third recess, and the fourth stack of nanosheets are in an active device region;
• and the passive device region and the active device region are separated by the second stack of nanosheets;
• forming a first diffusion region of a first passive device in the first recess;
• a first source/drain (S/D) region of a first nanosheet transistor in the second recess;
• and a second S/D region of the first nanosheet transistor in the third recess, wherein the first diffusion region and the first and the second S/D region are adjacent to the first set of nanosheets;
• forming a doped region on top of the first diffusion region and an interlevel dielectric (ILD) layer on top of the first and the second S/D region of the first nanosheet transistor;
• and
• forming a second diffusion region of the first passive device on top of the doped region;
• a third S/D region of a second nanosheet transistor on top of the first S/D region of the first nanosheet transistor;
• and a fourth S/D region of the second nanosheet transistor on top of the second S/D region of the first nanosheet transistor,
• wherein the active device region and the passive device region are separated by a first single diffusion break;
• wherein the first and the second diffusion region are vertically separated by the doped region;
• and wherein the third and the fourth S/D region of the second nanosheet transistor are separated from the first and the second S/D region, respectively, of the first nanosheet transistor by the ILD layer.