US 12,740,143 B2 · Reconfigurable complementary metal oxide semiconductor device and method

Abstract

Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).

Claims20

Dependent claims

A method comprising:

providing a device comprising:
an N-type field effect transistor and a P-type field effect transistor, wherein the N-type field effect transistor and the P-type field effect transistor comprise threshold voltage-programmable field effect transistors, are electrically connected in parallel, and have electrically connected gates;
and
concurrently programming threshold voltages of the N-type field effect transistor and the P-type field effect transistor.

1 more element

A method comprising:

providing a device comprising:
an N-type field effect transistor and a P-type field effect transistor, wherein the N-type field effect transistor and the P-type field effect transistor comprise threshold voltage-programmable field effect transistors, are electrically connected in parallel between an output node and a ground node, and have electrically connected gates, and wherein the electrically connected gates are further electrically connected to an input node;
and
concurrently programming threshold voltages of the N-type field effect transistor and the P-type field effect transistor.

1 more element

A method comprising:

providing a device comprising:
an N-type ferroelectric field effect transistor and a P-type ferroelectric field effect transistor electrically connected in parallel, and have electrically connected gates;
and
concurrently programming threshold voltages of the N-type ferroelectric field effect transistor and the P-type ferroelectric field effect transistor.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

18/452,637Filed 21 Aug 2023 · division

Priority

7 Jan 2021

Published

US 2023/0395605 A17 Dec 2023

Granted

15 Sep 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 84/907
Comprising field effect technology: cMOS gate arrays
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors

Reconfigurable complementary metal oxide semiconductor device and method

Life of this patent

Reconfigurable complementary metal oxide semiconductor device and method

Life of this patent

Abstract

Claims20