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US 12,740,141 B2Granted
H-bridge command circuit
AssigneeSTMicroeletronics S.r.l.
InventorsPhilippe Bienvenu, Julia Castellan, Antonio Calandra
Life of this patent
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Abstract
An integrated monolithic H-bridge is formed in a bulk semiconductor region. A first branch includes a first vertical MOS transistor and a second lateral MOS transistor integrated in the bulk semiconductor region. The first vertical MOS transistor and the second lateral MOS transistor are coupled in series. A second branch includes a third vertical MOS transistor and a fourth lateral MOS transistor integrated in the bulk semiconductor region. The third vertical MOS transistor and the fourth lateral MOS transistor are coupled in series and the first and second branches being coupled in parallel.
Claims20
A DC current motor command system comprising:
- a DC current motor;
- and
- an integrated monolithic H-bridge comprising:
- a bulk semiconductor region;
- a first branch comprising a first vertical MOS transistor and a second lateral MOS transistor integrated in the bulk semiconductor region, the first vertical MOS transistor and the second lateral MOS transistor being coupled in series;
- and
- a second branch comprising a third vertical MOS transistor and a fourth lateral MOS transistor integrated in the bulk semiconductor region, the third vertical MOS transistor and the fourth lateral MOS transistor being coupled in series and the first and second branches being coupled in parallel;
- wherein the command system is designed so that the first vertical MOS transistor of the H-bridge is turned on for an entire phase of rotation of the motor in one direction while the fourth lateral MOS transistor is controlled in pulse width modulation to vary a rotation speed of the motor or the second lateral MOS transistor is turned on for the entire phase of rotation of the motor in the one direction while the third vertical MOS transistor is controlled in pulse width modulation to vary the rotation speed of the motor.
5 more elements
An integrated monolithic H-bridge comprising:
- a bulk semiconductor region having a front side and a back side;
- a first vertical MOS transistor having current path extending from a first source/drain region at the front side of the bulk semiconductor region to a second source/drain region at the back side of the bulk semiconductor region;
- a second lateral MOS transistor integrated in the bulk semiconductor region and having first and second source/drain regions disposed at the front side of the bulk semiconductor region, the first source/drain region of the second lateral MOS transistor connected to the first source/drain region of the first vertical MOS transistor;
- a third vertical MOS transistor having a current path extending from a first source/drain region at the front side of the bulk semiconductor region to a second source/drain region at the back side of the bulk semiconductor region;
- a fourth lateral MOS transistor integrated in the bulk semiconductor region and having first and second source/drain regions disposed at the front side of the bulk semiconductor region, the first source/drain region of the fourth lateral MOS transistor connected to the first source/drain region of the third vertical MOS transistor;
- a high voltage node connected to the second source/drain of the first vertical MOS transistor and to the second source/drain of the third vertical MOS transistor;
- and
- a low voltage node connected to the second source/drain of the second lateral MOS transistor and to the second source/drain of the fourth lateral MOS transistor.
5 more elements
A semiconductor structure comprising:
- a bulk semiconductor region having a first conductivity type;
- an epitaxial layer of a second conductivity type disposed at a back side of the bulk semiconductor region;
- a first doped region of the first conductivity type extending from a front side of the bulk semiconductor region, the first doped region being more highly doped than the bulk semiconductor region;
- a second doped region of the second conductivity type disposed within the first doped region at the front side of the bulk semiconductor region;
- a first conductive region disposed at the front side of the bulk semiconductor region adjacent the second doped region, the first conductive region separated from the second doped region by an insulating layer;
- a third doped region of the second conductivity type disposed within the bulk semiconductor region at the front side of the bulk semiconductor region, the third doped region being laterally spaced from the second doped region;
- a fourth doped region of the second conductivity type disposed within the bulk semiconductor region at the front side of the bulk semiconductor region, the fourth third doped region being laterally spaced from the third doped region by a region of the first conductivity type;
- a second conductive region overlying the region of the first conductivity type and electrically insulated therefrom;
- and
- a buried layer disposed within the bulk semiconductor region beneath the third doped region, the fourth doped region, and the region of the first conductivity type, the buried layer not extending beneath the second doped region.
7 more elements
Dependencies are inferred from the claim text.