Semiconductor device having high-k gate dielectric layers

A semiconductor device comprising:

• a first gate structure including:
• a first interfacial insulating layer over a first area of a substrate,
• a first N-type high-k gate dielectric layer disposed over the first interfacial insulating layer, and
• a first gate electrode over first N-type high-k gate dielectric layer;
• a second gate structure comprising:
• a second interfacial insulating layer over a second area of the substrate,
• a first P-type high-k gate dielectric layer over the second interfacial insulating layer, and
• a second gate electrode over the first P-type high-k gate dielectric layer;
• a third gate structure including:
• a third interfacial insulating layer over a third area of the substrate,
• a second N-type high-k gate dielectric layer over the third interfacial insulating layer, and
• a third gate electrode over the second N-type high-k gate dielectric layer;
• and
• a fourth gate structure including:
• a fourth interfacial insulating layer over a fourth area of the substrate,
• a second P-type high-k gate dielectric layer over the fourth interfacial insulating layer, and
• a fourth gate electrode over the P-type high-k gate dielectric layer.

A semiconductor device comprising:

• a first gate structure including:
• a first interfacial insulating layer over a substrate,
• a first N-type high-k gate dielectric layer disposed over the first interfacial insulating layer, and
• a first gate electrode over first N-type high-k gate dielectric layer;
• a second gate structure comprising:
• a second interfacial insulating layer over the substrate,
• a first P-type high-k gate dielectric layer over the second interfacial insulating layer,
• a P-type dipole doped layer over the first P-type high-k gate dielectric layer, and
• a second gate electrode over the P-type dipole doped layer;
• and
• a third gate structure including:
• a third interfacial insulating layer over the substrate,
• a second N-type high-k gate dielectric layer over the third interfacial insulating layer,
• an N-type dipole doped layer over the second N-type high-k gate dielectric layer, and
• a third gate electrode over the N-type dipole doped layer.