Volumeless threshold voltage tuning for stacked device structures

A method comprising:

• forming a first lower transistor, a second lower transistor, a third lower transistor, and a fourth lower transistor, wherein the forming includes:
• forming a gate dielectric layer in a group of transistor regions that includes a first lower transistor region, a second lower transistor region, a third lower transistor region, and a fourth lower transistor region,
• forming a first patterned dipole dopant source layer and a second patterned dipole dopant source layer over the gate dielectric layer, wherein the first patterned dipole dopant source layer has a first pattern, the second patterned dipole dopant source lay er has a second pattern, and the second pattern is different than the first pattern, such that the first patterned dipole dopant source layer is over the gate dielectric layer in a first subgroup of the group of transistor regions, the second patterned dipole dopant source layer is over the gate dielectric layer in a second subgroup of the group of transistor regions, and the first subgroup of the group of transistor regions is different than the second subgroup of the group of transistor regions,
• performing a first thermal drive-in process that drives a first dipole into the gate dielectric layer from the first patterned dipole dopant source layer and a second thermal drive-in process that drives a second dipole dopant into the gate dielectric layer from the second patterned dipole dopant source layer, and
• after removing the first patterned dipole dopant source layer and the second patterned dipole dopant source layer, forming a gate electrode layer over the gate dielectric layer in the first lower transistor region, the second lower transistor region, the third lower transistor region, and the fourth lower transistor region;
• and
• forming a first upper transistor over the first lower transistor, a second upper transistor over the second lower transistor, a third upper transistor over the third lower transistor, and a fourth upper transistor over the fourth lower transistor.

A method comprising:

• forming a first gate opening that exposes a first channel structure of a first transistor, a second gate opening that exposes a second channel structure of a second transistor, a third gate opening that exposes a third channel structure of a third transistor, and a fourth gate opening that exposes a fourth channel structure of a fourth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor belong to a same level of a stacked transistor structure;
• forming a high-k dielectric layer over the first channel structure, the second channel structure, the third channel structure, and the fourth channel structure, wherein the high-k dielectric layer partially fills the first gate opening, the second gate opening, the third gate opening, and the fourth gate opening;
• performing a dipole engineering process on the high-k dielectric layer to provide the first transistor with a first high-k dielectric, the second transistor with a second high-k dielectric, the third transistor with a third high-k dielectric, and the fourth transistor with a fourth high-k dielectric, wherein the dipole engineering process includes:
• forming a first patterned dipole dopant source layer and a second patterned dipole dopant source layer over the high-k dielectric layer, wherein the first patterned dipole dopant source layer has a first pattern, the second patterned dipole dopant source layer has a second pattern, and the second pattern is different than the first pattern, such that the first patterned dipole dopant source layer is over the high-k dielectric layer of a first subgroup of a group of transistors, the second patterned dipole dopant source layer is over the high-k dielectric layer of a second subgroup of the group of transistors, the first subgroup of the group of transistors is different than the second subgroup of the group of transistors, and the group of transistors includes the first transistor, the second transistor, the third transistor, and the fourth transistor,
• performing a first thermal drive-in process that drives a first dipole into the high-k dielectric layer from the patterned first dipole dopant source layer and a second thermal drive-in process that drives a second dipole dopant into the high-k dielectric layer from the patterned second dipole dopant source layer, and
• removing the first patterned dipole dopant source layer and the second patterned dipole dopant source layer;
• and
• forming a gate electrode layer over the first high-k dielectric, the second high-k dielectric, the third high-k dielectric, and the fourth high-k dielectric, wherein the gate electrode layer fills a remainder of the first gate opening, the second gate opening, the third gate opening, and the fourth gate opening.