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US 12,740,126 B2Granted
Power semiconductor device and method of manufacturing same
AssigneeDB HiTek Co., Ltd.
InventorsMin Su Cho, Dae Il Kim, Ji Houn Jung, Hee Sub Lee, Ung Bi Son, Jun Hyeok Lee
Life of this patent
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Abstract
Proposed are a power semiconductor device and a method of manufacturing the same seeking to increase a current path area and to capture electrons trapped between a gate electrode and a drain electrode to prevent current collapse effects by forming a plurality of hole injection regions spaced apart from each other at the bottom of the drain electrode.
Claims17
A power semiconductor device, comprising:
- a substrate;
- a channel layer having a first nitride-based semiconductor layer and disposed on the substrate;
- a barrier layer disposed on the channel layer and having a second nitride-based semiconductor layer that is different from the first nitride-based semiconductor layer of the channel layer;
- a capping layer having an impurity doped region of a first conductivity type and disposed on the barrier layer;
- a gate electrode disposed on the capping layer;
- a plurality of hole injection regions, each having an impurity doped region of a first conductivity type, each being laterally spaced apart from another on the barrier layer;
- and
- a drain electrode in contact with the plurality of hole injection regions,
- wherein the drain electrode comprises a plurality of protruding regions, each being disposed at a bottom of the drain electrode in a space between the plurality of hole injection regions, and
- wherein an upper surface of the channel layer below each of the plurality of hole injection regions is disposed at a higher position than an upper surface of the channel layer below each of the plurality of protruding regions.
7 more elements
A power semiconductor device, comprising:
- a substrate;
- a channel layer having a first nitride-based semiconductor layer and disposed on the substrate;
- a barrier layer disposed on the channel layer and having a second nitride-based semiconductor layer that is different from the first nitride-based semiconductor layer of the channel layer;
- a capping layer having an impurity doped region of a first conductivity type and disposed on the barrier layer;
- a gate electrode disposed on the capping layer;
- a plurality of hole injection regions, each having an impurity doped region of a first conductivity type and laterally disposed apart from another on the barrier layer;
- a source electrode disposed apart from the gate electrode;
- and
- a drain electrode disposed apart from the gate electrode and including a plurality of protruding regions, each being disposed in a space between the plurality of hole injection regions,
- wherein an upper surface of the channel layer below each of the plurality of hole injection regions is disposed at a higher position than an upper surface of the channel layer below each of the plurality of protruding regions.
7 more elements
A method of manufacturing a power semiconductor device, the method comprising:
- forming a channel layer having a first nitride-based semiconductor layer on a substrate;
- forming a barrier layer having a second nitride-based semiconductor layer that is different from the first nitride-based semiconductor layer on the channel layer;
- forming a capping layer of a first conductivity type on the barrier layer;
- forming a plurality of hole injection regions on the barrier layer apart from the capping layer;
- forming a first insulating film layer on the barrier layer to cover the capping layer and the plurality of hole injection regions;
- and
- forming a source electrode and a drain electrode after etching the first insulating film layer.
4 more elements
Dependencies are inferred from the claim text.