US 12,740,115 B2 · Ultra-scaled transistor devices to enable cell size scaling

Abstract

Narrow-channel, non-planar transistors and their manufacture on integrated circuit dies. A method includes forming channel portions of transistors from sidewall spacers by removing backbone features and coupling a gate structure, a source, and a drain to the channel portions. An integrated circuit die includes a gate structure, a source, and a drain coupled to pair-symmetric channel portions with sidewalls of differing heights. A method includes iteratively etching away portions of semiconductor material not covered by a mask or a passivation layer, revealing a channel portion by removing the mask and passivation layer, and coupling a gate structure, a source, and a drain to the channel portion. An integrated circuit die includes a gate structure, a source, and a drain coupled to a channel portion with vertically alternating, greater and lesser widths.

Claims10

Dependent claims

An integrated circuit (IC) die, comprising:

a substrate comprising a semiconductor material;
a fin consisting of the semiconductor material, and over the substrate, the semiconductor material of the fin having a first width at a first height over the substrate, a second width at a second height over the substrate and above the first height, and a third width at a third height over the substrate and above the second height, wherein the first and third widths are greater than the second width;
and
a gate structure, a source, and a drain coupled to a channel portion of the fin, wherein the IC die comprises, or is thermally coupled to, a cooling structure, the cooling structure to remove heat from the IC die to achieve an operating temperature below −25° C.

1 more element

Dependencies are inferred from the claim text.

Ultra-scaled transistor devices to enable cell size scaling

Life of this patent

Ultra-scaled transistor devices to enable cell size scaling

Life of this patent

Abstract

Claims10