SiC VJFET with edge termination for dual tilted gate implants
AssigneeWolfspeed, Inc.
InventorsRahul R. Potera, Thomas Harrington, Madankumar Sampath, Steven Rogers
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AssigneeWolfspeed, Inc.
InventorsRahul R. Potera, Thomas Harrington, Madankumar Sampath, Steven Rogers
Estimating the term…
A semiconductor device includes an active region comprising a plurality of alternating trenches and mesas in an epitaxial layer, the plurality of alternating trenches and mesas extending in a first direction, and an edge termination region adjacent the active region and including a first edge termination region and a second edge termination region. The edge termination region includes first and second guard ring trenches adjacent the active region that are separated by a termination mesa that extends in the first direction in the first edge termination region and extends in a second direction, perpendicular to the first direction, in the second edge termination region. The termination mesa has a first width in the first edge termination region and the termination mesa has a second width in the second edge termination region that is different from the first width.
A semiconductor device, comprising:
A semiconductor device, comprising:
A method of forming a semiconductor device, comprising:
A method of forming a semiconductor device, comprising:
A method of forming a semiconductor device, comprising:
Dependencies are inferred from the claim text.