Transistors with mitigated free body effect

An electronic device comprising:

• a first vertical transistor having a first gate separated from a first channel structure by a first gate dielectric;
• a second vertical transistor having a second gate separated from a second channel structure by a second gate dielectric;
• a conductive shield between the first channel structure and the second channel structure;
• and
• a conductive body shorted to the conductive shield and positioned between the first channel structure and the second channel structure, the conductive body contacting the first channel structure and the second channel structure, wherein the conductive shield is parallel to the first gate and the first gate is parallel to the second gate, the conductive shield having a length equal to that of the first gate.

A memory device comprising:

• data lines;
• an array of memory cells, the memory cells arranged having a first set of memory cells coupled to a first data line of the data lines and a second set of memory cells coupled to a second data line of the data lines, the first set including:
• a first vertical transistor having a first gate separated from a first channel structure by a first gate dielectric, the first channel structure connecting a lower source/drain to an upper source/drain of the first vertical transistor, the first vertical transistor coupled to and extending from a first data line of the data lines;
• a second vertical transistor having a second gate separated from a second channel structure by a second gate dielectric, the second channel structure connecting a lower source/drain to an upper source/drain of the second vertical transistor, the second vertical transistor coupled to and extending from the first data line;
• a conductive shield between the first channel structure and the second channel structure at a vertical level between the lower source/drains and the upper source/drains of the first and second vertical transistors;
• and
• a conductive body shorted to the conductive shield and positioned between the first channel structure and the second channel structure, the conductive body contacting the first channel structure above a bottom end of the lower source/drain of the first vertical transistor and contacting the second channel structure above a bottom end of the lower source/drain of the second vertical transistor;
• and
• access lines including a first access line coupled to the first gate and a second access line coupled to the second gate, the first access line being different from the second access line.

A method comprising:

• forming a first vertical transistor having a first gate separated from a first channel structure by a first gate dielectric such that the first channel structure connects a lower source/drain to an upper source/drain of the first vertical transistor;
• forming a second vertical transistor having a second gate separated from a second channel structure by a second gate dielectric such that the second channel structure connects a lower source/drain to an upper source/drain of the second vertical transistor;
• forming a conductive body contacting the first channel structure above a bottom end of the lower source/drain of the first vertical transistor and contacting the second channel
• structure above a bottom end of the lower source/drain of the second vertical transistor;
• and
• forming a conductive shield between the first channel structure and the second channel structure such that the conductive shield is shorted to the conductive body and is positioned between the first channel structure and the second channel structure at a vertical level between the lower source/drains and the upper source/drains of the first and second vertical transistors.

A method comprising:

• forming a first vertical transistor having a first gate separated from a first channel structure by a first gate dielectric;
• forming a second vertical transistor having a second gate separated from a second channel structure by a second gate dielectric;
• forming a conductive body contacting the first channel structure and the second channel structure;
• and
• forming a conductive shield between the first channel structure and the second channel structure such that the conductive shield is shorted to the conductive body and is positioned between the first channel structure and the second channel structure, wherein the method includes, after forming the first vertical transistor and the second vertical transistor:
• forming a trench between the first vertical transistor and the second vertical transistor, the trench ending on a dielectric region above a conductive line on which the first vertical transistor and the second vertical transistor are formed;
• forming a shield dielectric in the trench, leaving an opening in the trench;
• forming a sacrificial dielectric on the shield dielectric;
• removing the sacrificial dielectric and a portion of the shield dielectric, forming a second opening defined by the dielectric region above the conductive line, the first channel structure, and the second channel structure;
• and
• forming the conductive body in the second opening such that the conductive body contacts the first channel structure and the second channel structure.