Semiconductor structure and forming method thereof

A semiconductor structure, comprising:

• a substrate;
• a gate structure, located on the substrate;
• a source/drain doped area, located in the substrate on two sides of the gate structure;
• a contact etch stop layer, located on the substrate between the source/drain doped area and the gate structure and arranged opposite to a side wall of the gate structure, a gap being provided between the contact etch stop layer and the side wall of the gate structure;
• a source/drain plug, located at a top of the source/drain doped area and contacting the source/drain doped area;
• and
• a top dielectric layer, filling between the source/drain plugs, the top dielectric layer further filling the gap and the top dielectric layer filling the gap serving as a spacer, or the top dielectric layer sealing a top of the gap to form an air gap, and a material of the top dielectric layer being a low k dielectric material or an ultra-low k dielectric material;
• a bottom dielectric layer, located on the substrate at a side of the gate structure, the bottom dielectric layer covering the source/drain doped area, wherein the source/drain plug comprises:
• a bottom source/drain plug, running through the bottom dielectric layer above the source/drain doped area and contacting the source/drain doped area;
• and
• a top source/drain plug, located on the bottom source/drain plug and contacting the bottom source/drain plug;
• a source/drain cap layer, located between a top of the bottom source/drain plug and the top dielectric layer;
• a gate plug, located at a top of the gate structure and contacting the gate structure;
• and
• a gate cap layer, located between the top of the gate structure and the top dielectric layer, wherein the top dielectric layer fills between the source/drain plug and the gate plug.