Integrated circuit device

An integrated circuit device comprising:

• a substrate comprising a cell array region and a peripheral circuit region having a plurality of line trenches that extend in a first horizontal direction in the peripheral circuit region;
• a plurality of buried conductive lines that are each respectively arranged inside a respective line trench of the plurality of line trenches;
• a plurality of first lower capacitor contacts that are each in contact with a respective buried conductive line of a first group of buried conductive lines selected from among the plurality of buried conductive lines;
• and
• a plurality of second lower capacitor contacts that are each in contact with a respective buried conductive line of a second group of buried conductive lines selected from among the plurality of buried conductive lines,
• wherein the first group of buried conductive lines and the second group of buried conductive lines are arranged to alternate between a buried conductive line of the first group of buried conductive lines and a buried conductive line of the second group of buried conductive lines along a second horizontal direction perpendicular to the first horizontal direction.

An integrated circuit device comprising:

• a substrate comprising a cell array region and a peripheral circuit region;
• a buried capacitor structure located inside the substrate in the peripheral circuit region;
• an upper capacitor structure disposed above the substrate in the peripheral circuit region;
• a first conductive pad and a second conductive pad, which are each connected to the upper capacitor structure above the substrate;
• a plurality of first lower capacitor contacts configured to connect the first conductive pad to the buried capacitor structure;
• and
• a plurality of second lower capacitor contacts configured to connect the second conductive pad to the buried capacitor structure,
• wherein the buried capacitor structure comprises:
• a first ion implantation region located in an upper portion of the substrate;
• a plurality of lower capacitor dielectric films with each lower capacitor dielectric film configured to respectively cover inner walls of a respective line trench of a plurality of line trenches that extend in a first horizontal direction and cross the first ion implantation region;
• and
• a plurality of buried conductive lines that each partially fill a respective line trench of the plurality of line trenches and that are each respectively disposed on a respective lower capacitor dielectric film of the plurality of lower capacitor dielectric films,
• wherein the plurality of first lower capacitor contacts are each respectively in contact with a respective buried conductive line of the plurality of buried conductive lines, and the plurality of second lower capacitor contacts are in contact with the first ion implantation region.