US 12,740,066 B1Granted

Split memory array to reduce bit-line capacitance

AssigneeKepler Computing Inc.

InventorsRajeev Kumar Dokania, Mustansir Yunus Mukadam, Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Sasikanth Manipatruni

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Abstract

A memory array is split into two or more subarrays with bit-line multiplexers or selection circuitries between the subarrays. Bit-line routes are split along the subarrays via the selection circuitries. The selection circuitries decouple the bit-lines into separate bit-line routes which allow the capacitance on the bit-lines to reduce as parasitic capacitance from the bit-line routes is reduced and bit-line is not driving all the access transistors in a row of the memory array. By using one of the two split bit-lines as the main bit-line, the main bit-line has lower capacitance resulting in faster sensing and better sensing margin since the voltage for sensing on the bit-lines is developed faster, as also larger signal is developed due to lower parasitic capacitance. Further, the access transistor of the selected row can be switched faster which results in higher memory performance. Polarization density requirements also reduce by lowering the parasitic capacitance.

Claims17

Dependent claims

An apparatus comprising:

a first array comprising first bit-cells arranged in first rows and in first columns, wherein the first rows are orthogonal to the first columns, wherein the first array having a first set of bit-lines, and wherein an individual first row of the first rows has an individual first bit-line of the first set of bit-lines;
a second array comprising second bit-cells that are arranged in second rows and second columns, wherein the second rows are orthogonal to the second columns, wherein the second array having a second set of bit-lines, and wherein an individual second row of the second rows has an individual second bit-line of the second set of bit-lines;
and
a selection circuitry positioned between the first array and the second array, wherein the selection circuitry is operable to pass a signal to one of the individual first bit-line or the individual second bit-line according to one or more controls, wherein the selection circuitry comprises a first transistor controllable by a first control of the one or more controls and a second transistor controllable by a second control of the one or more controls, and wherein the first control and the second control are complementary of each other.

1 more element

Dependencies are inferred from the claim text.