NAND plane boundary shrink

A method for forming adjacent planes in a memory die, the method comprising:

• forming a first plane having a first stack of alternating insulating layers and conductive layers in x-y planes and a second stack of alternating insulating layers and conductive layers in the x-y planes, the first plane having a first mid-plane word line hookup region between the first stack and the second stack;
• forming a second plane having a third stack of alternating insulating layers and conductive layers the x-y planes and a fourth stack of alternating insulating layers and conductive layers in the x-y planes, the second plane having a second mid-plane word line hookup region between the third stack and the fourth stack, wherein the second plane is adjacent to the first plane in an x-direction;
• forming a dummy array region between the first plane and the second plane in the x-direction, including forming alternating layers of a first material and a second material that is a different material than the first material, the alternating layers of the first material and the second material in the x-y planes;
• forming a first electrical isolation structure between the dummy array region and the first plane;
• forming a second electrical isolation structure between the dummy array region and the second plane;
• forming a first plurality of bit lines over the first plane, wherein each bit line of the first plurality of bit lines extends in a y-direction;
• and
• forming a second plurality of bit lines over the second plane, wherein each bit line of the second plurality of bit lines extends in the y-direction.

A NAND memory device comprising:

• a first plane having a first stack of alternating insulating layers comprising a first insulating material and conductive layers comprising a conductive material and a second stack of alternating insulating layers comprising the first insulating material and conductive layers comprising the conductive material, the first stack having a first staircase structure adjacent to the second stack, the second stack having a second staircase structure adjacent to the first stack;
• a second plane having a third stack of alternating insulating layers comprising the first insulating material and conductive layers comprising the conductive material and a fourth stack of alternating insulating layers comprising the first insulating material and conductive layers comprising the conductive material, the third stack having a third staircase structure adjacent to the fourth stack, the fourth stack having a fourth staircase structure adjacent to the third stack;
• a dummy array region between the first plane and the second plane, the dummy array region having a stack of alternating first layers comprising the first insulating material and second layers comprising a second insulating material;
• a first slit trench fill structure between the dummy array region and the first plane, wherein the first slit trench fill structure comprises an insulator between the dummy array region and the second stack;
• and
• a second slit trench fill structure between the dummy array region and the second plane, wherein the second slit trench fill structure comprises an insulator between the dummy array region and the third stack;
• wherein extending in sequentially a first direction are the first stack, the first staircase structure, the second staircase structure, the second stack, the first slit trench fill structure, the dummy array region, the second slit trench fill structure, the third stack, the third staircase structure, the fourth staircase structure, and the fourth stack.