One time programming memory cell with gate-all-around transistor for physically unclonable function technology

An antifuse-type OTP memory cell for a physically unclonable function technology, the antifuse-type OTP memory cell comprising:

• a first nanowire;
• a first gate structure comprising a first spacer, a second spacer, a first gate dielectric layer and a first gate layer, wherein a central region of the first nanowire is surrounded by the first gate dielectric layer, the first gate dielectric layer is surrounded by the first gate layer, the first gate layer is connected with an antifuse control line, a first side region of the first nanowire is surrounded by the first spacer, and a second side region of the first nanowire is surrounded by the second spacer;
• a first drain/source structure electrically contacted with a first terminal of the first nanowire;
• a second nanowire;
• a second gate structure comprising a third spacer, a fourth spacer, a second gate dielectric layer and a second gate layer, wherein a central region of the second nanowire is surrounded by the second gate dielectric layer, the second gate dielectric layer is surrounded by the second gate layer, the second gate layer is connected with the antifuse control line, a first side region of the second nanowire is surrounded by the third spacer, and a second side region of the second nanowire is surrounded by the fourth spacer;
• a second drain/source structure electrically contacted with a second terminal of the first nanowire and a first terminal of the second nanowire;
• a third drain/source structure electrically contacted with a second terminal of the second nanowire;
• a first select transistor comprising a first drain/source terminal, a gate terminal and a second drain/source terminal, wherein the first drain/source terminal of the first select transistor is connected with a first bit line, and the gate terminal of the first select transistor is connected with a word line;
• a first following transistor comprising a first drain/source terminal, a gate terminal and a second drain/source terminal, wherein the first drain/source terminal of the first following transistor is connected with the second drain/source terminal of the first select transistor, the gate terminal of the first following transistor is connected with a following control line, and the second drain/source terminal of the first following transistor is connected with the first drain/source structure;
• a second following transistor comprising a first drain/source terminal, a gate terminal and a second drain/source terminal, wherein the first drain/source terminal of the second following transistor is connected with the third drain/source structure, and the gate terminal of the second following transistor is connected with the following control line;
• and,
• a second select transistor comprising a first drain/source terminal, a gate terminal and a second drain/source terminal, wherein the first drain/source terminal of the second select transistor is connected with the second drain/source terminal of the second following transistor, the gate terminal of the second select transistor is connected with the word line, and the second drain/source terminal of the second select transistor is connected with a second bit line.