Process method for improving SRAM operating speed

A process method for improving an SRAM operating speed, at least comprising:

• step I, providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and an active region on the substrate;
• forming a low voltage region, a medium voltage region, and a high voltage region in the active region;
• and forming a low voltage PMOS active region and a low voltage NMOS active region in the low voltage region;
• forming an STI region between the low voltage PMOS active region and the low voltage NMOS active region, and between the medium voltage region and the high voltage region in the active region;
• and forming an oxide layer and a high temperature oxide (HTO) film layer to cover the semiconductor structure;
• step II, forming a hard mask on the HTO film layer;
• step III, spin-coating the hard mask with a photoresist layer, and performing photolithography to expose the hard mask on the low voltage region in the active region;
• step IV, etching off the exposed hard mask on the low voltage region of the active region and the HTO film layer and the oxide layer below the hard mask, thereby exposing the low voltage PMOS active region and the low voltage NMOS active region and exposing the STI region between the low voltage PMOS active region and the low voltage NMOS active region, wherein an etching rate is controlled so that a first height of the STI region between the low voltage PMOS active region and the low voltage NMOS active region is less than a height of each of the low voltage PMOS active region and the low voltage NMOS active region;
• and
• step V, removing a remaining hard mask unexposed after the etching off.