Memory device and method for manufacturing the same

A memory device, comprising:

• a first active area and a second active area extending in a first direction and arranged in a second direction perpendicular to the first direction, wherein each of the first active area and the second active area comprises channel layers and source/drain features;
• a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure extending in the second direction and arranged in the first direction, wherein the first gate structure and the fourth gate structure are across the first active area in a top view, and the second gate structure and the third gate structure are across the first active area and the second active area in the top view;
• a first dielectric structure and a second dielectric structure across the second active area and extending in the second direction, wherein a top surface of the first dielectric structure and a top surface of the second dielectric structure are higher than top surfaces of the source/drain features;
• and
• a dielectric layer under the second active area, the first dielectric structure and the second dielectric structure, wherein the first dielectric structure and the second dielectric structure interface with the dielectric layer,
• wherein the second gate structure and the third gate structure are between the first dielectric structure and the second dielectric structure in the first direction,
• wherein the first dielectric structure is aligned with the first gate structure in the second direction and the second dielectric structure is aligned with the fourth gate structure in the second direction.

A memory device, comprising:

• a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor arranged in a first direction and share a first active area, wherein the first active area comprises first channel layers, second channel layers, third channel layers, and fourth channel layers;
• a first PMOS transistor, a second PMOS transistor, a first dielectric structure, and a second dielectric structure arranged in the first direction and sharing a second active area, wherein the first active area and the second active area arranged in a second direction perpendicular to the first direction, wherein the second active area comprises fifth channel layers and sixth channel layers, wherein the first active area is separated from the second active area in the second direction, wherein in a cross-sectional view, a top surface of the first dielectric structure is higher than topmost surfaces of the fifth channel layers and the sixth channel layers;
• a first gate structure extending across the first active area and aligned with the first dielectric structure in the second direction;
• a second gate structure extending across the first active area and the second active area in the second direction;
• a third gate structure extending across the first active area and the second active area in the second direction;
• and
• a fourth gate structure extending across the first active area and aligned with the second dielectric structure in the second direction.