Memory decision feedback equalizer

A memory device comprising:

• a data (DQ) receiver of the memory device, wherein the DQ receiver is configured to receive serial data via a bus able to be interconnected to a host;
• a decision feedback equalizer of the memory device, wherein the decision feedback equalizer comprises:
• feedback circuitry configured to receive the serial data from respective circuitry of a plurality of circuitry after the serial data has been corrected of at least some amount of inter-symbol interference;
• a plurality of taps comprising a first tap, a second tap, a third tap, and a fourth tap;
• and
• the plurality of circuitry comprising first circuitry, second circuitry, third circuitry, and fourth circuitry, wherein each respective circuitry of the plurality of circuitry is coupled to the feedback circuitry via each respective tap of the plurality of taps, and wherein each respective circuitry of the plurality of circuitry is operable to receive respective bits of the serial data corrected of the at least some amount of inter-symbol interference from the feedback circuitry in a previous bit order for that respective circuitry;
• and
• an input/output interface comprising a plurality of data transceivers each comprising a respective DQ receiver and a respective decision feedback equalizer, wherein a respective data transceiver of the plurality of data transceivers comprises the DQ receiver and the decision feedback equalizer, and wherein the plurality of data transceivers receives one of each of a plurality of data signals.

A memory device comprising:

• a data (DQ) receiver configured to couple to a bus to receive serial data from a host;
• a decision feedback equalizing circuitry comprising:
• a plurality of taps configured to feedback the serial data after the serial data has been corrected of at least some amount of inter-symbol interference, wherein the plurality of taps comprises a first tap, a second tap, a third tap, and a fourth tap;
• and
• a plurality of circuitry configured to process four data bits at a four bit distortion correction level, wherein the plurality of circuitry comprises first circuitry, second circuitry, third circuitry, and fourth circuitry, wherein each respective circuitry of the plurality of circuitry is coupled to each respective tap of the plurality of taps, and wherein each respective circuitry of the plurality of circuitry is operable to receive respective bits of the serial data according to a previous bit order for that respective circuitry;
• and
• an input/output interface comprising a plurality of data transceivers each comprising a respective DQ receiver and a respective decision equalizing circuitry, wherein a respective data transceiver of the plurality of data transceivers comprises the DQ receiver and the decision feedback equalizing circuitry, and wherein the plurality of data transceivers receives one of each of a plurality of data signals.

A memory device comprising:

• an input/output interface comprising a first data transceiver and a second data transceiver,
• wherein the first data transceiver comprises:
• a first data (DQ) receiver configured to receive first serial data;
• and
• a first decision feedback equalizer comprising:
• first feedback circuitry configured to receive the first serial data after the first serial data has been corrected of at least some amount of inter-symbol interference;
• a first plurality of taps;
• and
• a first plurality of circuitry, wherein each respective circuitry of the first plurality of circuitry is coupled to the first feedback circuitry via each respective tap of the first plurality of taps, and wherein each respective circuitry of the first plurality of circuitry is operable to receive respective bits of the first serial data from the first feedback circuitry according to a previous bit order for that respective circuitry implemented by the first plurality of taps;
• and
• wherein the second data transceiver comprises:
• a second data (DQ) receiver configured to receive second serial data;
• and
• a second decision feedback equalizer comprising:
• second feedback circuitry configured to receive the second serial data after the second serial data has been corrected of at least some amount of inter-symbol interference;
• a second plurality of taps;
• and
• a second plurality of circuitry, wherein each respective circuitry of the second plurality of circuitry is coupled to the second feedback circuitry via each respective tap of the second plurality of taps, and wherein each respective circuitry of the second plurality of circuitry is operable to receive respective bits of the second serial data from the second feedback circuitry according to a previous bit order for that respective circuitry implemented by the second plurality of taps.