ADC offset correction with partial unscrambled data

A method comprising:

• accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;
• destabilizing a clock data recovery (CDR) component to generate a random frequency offset:
• instructing an analog-to-digital converter (ADC) to sample the training sequence, using a set of clock signals generated by a phase interpolator (PI) using the CDR component based on the random frequency offset, to generate a set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions;
• and
• calibrating an ADC offset based on the training sequence that has been sampled by the ADC using the set of clock signals generated by the PI using the CDR component based on the random frequency offset.

A non-transitory computer-readable medium comprising computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

• accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;
• destabilizing a clock data recovery (CDR) component to generate a random frequency offset;
• instructing an analog-to-digital converter (ADC) to sample the training sequence, using a set of clock signals generated by a phase interpolator (PI) using the CDR component based on the random frequency offset, to generate a set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions;
• and
• calibrating an ADC offset based on the training sequence that has been sampled by the ADC using the set of clock signals generated by the PI using the CDR component based on the random frequency offset.