Pattern transition filter for clock data recovery

A system, comprising:

• a sampling circuit, wherein the sampling circuit is configured to:
• receive a data signal including a first data symbol and a second data symbol, wherein each of the first data symbol and the second data symbol is at one of a first level, a second level, and a third level;
• sample the first data symbol at a first sampling time to generate a first data bit and a second data bit;
• sample the data signal at a second sampling time to generate an edge bit;
• and
• sample the second data symbol at a third sampling time to generate a third data bit and a fourth data bit;
• a phase detector;
• and
• a transition filter coupled between the sampling circuit and the phase detector, wherein the transition filter comprises:
• a first gating circuit configured to receive the first data bit;
• a second gating circuit configured to receive the third data bit;
• a third gating circuit configured to receive the edge bit;
• and
• a transition detector configured to:
• receive the first data bit, the second data bit, the third data bit, and the fourth data bit;
• and
• cause the first gating circuit, the second gating circuit, and the third gating circuit to pass the first data bit, the third data bit, and the edge bit, respectively, to the phase detector if the first data bit and the third data bit have different bit values and the second data bit and the fourth data bit have different bit values.

A method for transition filtering, comprising:

• receiving a data signal including a first data symbol and a second data symbol, wherein each of the first data symbol and the second data symbol is at one of a first level, a second level, and a third level;
• sampling the first data symbol at a first sampling time to generate a first data bit and a second data bit;
• sampling the data signal at a second sampling time to generate an edge bit;
• sampling the second data symbol at a third sampling time to generate a third data bit and a fourth data bit;
• detecting a transition between the first level and the third level between the first data symbol and the second data symbol;
• and
• passing the first data bit, the third data bit, and the edge bit to a phase detector in response to detecting the transition between the first level and the third level.