Phase interpolation circuit, circuit device, and oscillator

A phase interpolation circuit configured to generate an interpolation clock signal obtained by performing phase interpolation between a first clock signal and a second clock signal different in phase from the first clock signal, the phase interpolation circuit comprising:

• a current source circuit that is disposed between a first power supply node and a first node, and supplies the first node with a first current that flows when the first clock signal becomes active and a second current that flows when the second clock signal becomes active;
• a discharging transistor that is disposed between the first node and a second power supply node, and that is turned ON when the first clock signal and the second clock signal become inactive;
• a current control circuit configured to set a current ratio between the first current and the second current based on a phase interpolation signal that instructs a ratio of phase interpolation between the first clock signal and the second clock signal;
• and
• an output circuit configured to output the interpolation clock signal based on a signal at the first node.