On-chip test tone generator for built-in spur testing

Abstract

An apparatus is disclosed that implements an on-chip test tone generator for built-in spur testing. In an example aspect, the apparatus includes an integrated circuit with a test tone generator, at least one reference signal generator, and at least one signal propagation path. The test tone generator includes an amplitude control circuit. The at least one signal propagation path includes a transceiver path, a mixer, and a switch. The transceiver path is configured to be coupled to an antenna. The mixer has a first input coupled to the at least one reference signal generator. The switch is configured to selectively couple a second input of the mixer to the transceiver path or the amplitude control circuit of the at least one test tone generator.

Dependencies are inferred from the claim text.