Method for receiving two digital signals in a dual-polarization digital communication system

A method for receiving first and second digital signals, comprising first and second independent streams of oversampled and pulse-shaped baseband digital complex-valued samples, in a dual-polarization digital communication system utilizing first and second radio-frequency (RF) polarization channels, comprising

• receiving the first and second digital signals transmitted via the first and second radio-frequency (RF) polarization channels, wherein each of the first and second received digital signals comprises a stream of oversampled and pulse-shaped baseband digital complex-valued samples, and wherein each of the first and second received digital signals also includes a cross-polarization interference (XPI) component,
• jointly processing the first and second received digital signals for providing estimation and cancellation of the cross-polarization interference (XPI) components,
• wherein processing comprises estimation of a cross factor, and
• wherein processing further comprises estimation of each interfering component by means of the estimated cross factor and subtraction of each estimated interfering component from the corresponding received signal,
• wherein the processing step further comprises the following clock signals:
• a main clock signal, determining the fundamental frequency of the processing,
• an odd clock signal, being half the frequency of the main clock signal, having its rising edge synchronous with the rising edge of the main clock signal, and
• an even clock signal, being a shifted version of the odd clock signal, having its rising edge synchronous with the falling edge of the main clock signal, and
• wherein the processing step further comprises sequentially inputting the received samples of the first and second channels into first and second shift registers with equal even-number length (const_length_of_reg_1), wherein each shift register comprises delay elements, wherein the length (const_length_of_reg_1) is the number of delay elements, and wherein the shift registers are driven by the main clock signal,
• wherein the step of estimation of the cross factor further comprises inputting the oversampling factor used during sampling of the two received signals, and using it to compute the sampling correction factor by means of interpolation or extrapolation with a look-up table (LUT sampling) in Table 1 of the specification, and
• wherein the step of estimation of the cross factor further comprises the following steps:
• multiplying the output of the first delay element of the first shift register with the complex conjugate of the output of the first delay element of the second shift register, multiplying the output of the last delay element of the first shift register with the complex conjugate of the output of the last delay element of the second shift register, subtracting the result of the latter multiplication from the result of the former multiplication, adding the result to the output of a first single-element shift register, serving as an accumulator, being driven by the main clock signal, and having the result input to the first single-element shift register,
• sequentially feeding the received samples of the first channel into a first half-length shift register with length of half the value of the even-number length (const_length_of_reg_1) of the first shift register, wherein the first half-length shift register is driven by the odd clock signal, and sequentially feeding the received samples of the first channel into a second half-length shift register with length of half the value of the even-number length (const_length_of_reg_1) of the first shift register, wherein the second half-length shift register is driven by the even clock signal, multiplying the output of the first delay element of the first half-length shift register with the complex conjugate of the output of the first delay element of the second half-length shift register, multiplying the output of the last delay element of the first half-length shift register with the complex conjugate of the output of the last delay element of the second half-length shift register, subtracting the result of the latter multiplication from the result of the former multiplication, adding the result to the output of a second single-element shift register, serving as an accumulator, being driven by the even clock signal, and having the result input to the second single-element shift register,
• sequentially feeding the received samples of the second channel into a third half-length shift register with length of half the value of the even-number length (const_length_of_reg_1) of the first shift register, wherein the third half-length shift register is driven by the odd clock signal, and sequentially feeding the received samples of the second channel into a forth half-length shift register with length of half the value of the even-number length (const_length_of_reg_1) of the first shift register, wherein the forth half-length shift register is driven by the even clock signal, multiplying the output of the first delay element of the third half-length shift register with the complex conjugate of the output of the first delay element of the forth half-length shift register, multiplying the output of the last delay element of the third half-length shift register with the complex conjugate of the output of the last delay element of the forth half-length shift register, subtracting the result of the latter multiplication from the result of the former multiplication, adding the result to the output of a third single-element shift register, serving as an accumulator, being driven by the even clock signal, and having the result input to the third single-element shift register,
• taking the real values of the outputs of the second and third single-element shift registers, multiplying each of them with the sampling correction factor and with the constant (const_acc_auto) from the following equation:
• const_acc
• ⁢
• _auto
• =
• 2
• /
• (
• const_length
• ⁢
• _of
• ⁢
• _reg
• ⁢
• _
• ⁢
• 1
• -
• 2
• )
• ,
• and adding the two results together,
• computing the reciprocal value of the result of the latter addition by means of a look-up table (LUT reciprocal) of the reciprocal function, wherein the reciprocal function is defined as 1 divided by the argument of the function, and multiplying it with the output of the first single-element shift register and with the constant (const_acc_cross) from the following equation:
• const_acc
• ⁢
• _cross
• =
• 1
• /
• (
• const_length
• ⁢
• _of
• ⁢
• _reg
• ⁢
• _
• ⁢
• 1
• -
• 1
• )
• ,
• taking the real and imaginary values of the result of the latter multiplication, applying a look-up table (LUT function) for the function in the following equation:
• f
• ⁡
• (
• x
• )
• =
• Real
• ⁢
• {
• 1
• -
• 1
• -
• 4
• ⁢
• x
• 2
• 2
• ⁢
• x
• }
• on each of them, and respectively combining the two results to form a complex-valued number, being the estimate of the cross factor.