Synchronization circuit and method

A method for determining a timing error between a first signal and a second signal, the second signal being delayed compared to the first signal and having a different frequency compared to the first signal, the method comprising:

• receiving, by a time-to-digital converter (TDC), the first signal and a second signal;
• and
• measuring, using the TDC, a timing delay between the first signal and the second signal by activating the TDC between a rising edge of the first signal a successive rising edge of the second signal and otherwise deactivating the TDC to a lower power state as compared to the activated state.

A circuit for synchronizing a sampling device to at least one other sampling device, the sampling device and the at least one sampling device receiving a first clock signal CLK and receiving a desired output data rate ODR signal, the circuit comprising a time-to-digital converter (TDC) configured to receive the ODR signal as a first signal and to receive the first clock signal CLK as a second signal and to determine a timing delay between the ODR signal and the first clock signal CLK, wherein an output of the TDC is coupled to a synchronization circuit, the synchronization circuit being configured to receive the determined timing delay, to receive the ODR signal, and to receive the first clock signal CLK, and to output a second clock signal CLK2 that is synchronized to the ODR signal.