Digitally calibrated programmable clock phase generation circuit

A system, comprising:

• an integrated circuit, comprising
• a generating circuit comprising a gated ring oscillator, wherein the generating circuit is configured to provide an edge clock having a target phase within a clock period of an input clock and a having duty cycle,
• wherein the generating circuit does not include a delay locked loop (DLL), and
• wherein the duty cycle is other than 50/50 and the generating circuit is configured to provide the edge clock having the duty cycle by selectively turning the gated ring oscillator on and off based at least in part on a control signal.

A method for providing an edge clock, comprising:

• by a generating circuit:
• providing the edge clock having a target phase within a clock period of an input clock and having a duty cycle, wherein the generating circuit comprises a gated ring oscillator, and wherein the generating circuit does not include a delay locked loop (DLL);
• and
• when the duty cycle is other than 50/50, providing the edge clock having the duty cycle by selectively turning the gated ring oscillator on and off based at least in part on a control signal.