US 12,738,909 B2Granted

Current equalization circuitry for the folded branch of a rail-to-rail input ota with ab-class output stage

AssigneeSTMicroelectronics International N.V.

InventorLorenzo Giancristofaro

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Abstract

Described herein is an operational transconductance amplifier (OTA) with a constant current source that provides a constant current to a node. The OTA includes two input pairs of transistors: the first sources variable currents based on feedback and input voltages, while the second sinks variable currents also based on feedback and input voltages. A folded cascode arrangement includes two branches, with one branch including a Monticelli cell. A class-AB output stage is present, with its inputs connected across the Monticelli cell. Additionally, a bias stage mirrors and scales the constant current to generate control voltages. Within the folded cascode branches, compensation transistors are controlled by these control voltages, ensuring that various sourced and sunk variable currents are of equal magnitude, making the OTA input voltage independent.

Claims18

Dependent claims

An operational transconductance amplifier (OTA), comprising:

a constant current source configured to source a first constant current to a first node;
a first input pair of transistors comprising:
a first input transistor coupled between the first node and a third folded branch node, the first input transistor configured to source a first variable current to the third folded branch node based upon a feedback voltage;
and a second input transistor coupled between the first node and a fourth folded branch node, the second input transistor configured to source a second variable current to the fourth folded branch node based upon an input voltage;
a tail current source configured to sink a tail current from a second node;
a second input pair of transistors comprising:
a third input transistor coupled between a first folded branch node and the second node, the third input transistor configured to sink a third variable current from the first folded branch node based upon the feedback voltage;
and a fourth input transistor coupled between a second folded branch node and the second node, the fourth input transistor configured to sink a fourth variable current from the second folded branch node based upon the input voltage;
a folded cascode arrangement comprising:
a first folded cascode branch coupled to the first folded branch node and the third folded branch node;
a second folded cascode branch coupled to the second folded branch node and the fourth folded branch node;
wherein the second folded cascode branch includes a Monticelli cell coupled between the second folded branch node and the fourth folded branch node;
a class-AB output stage having inputs coupled across the Monticelli cell;
and
a bias stage configured to mirror and scale the first constant current and the tail current to produce first and second control voltages;
wherein the folded cascode arrangement includes, within the first folded cascode branch:
a first tail generator transistor controlled by the first control voltage to source a fifth variable current to the first folded branch node, the fifth variable current being equal in magnitude to the third variable current;
and
a second tail generator transistor controlled by the second control voltage to sink a sixth variable current from the third folded branch node, the sixth variable current being equal in magnitude to the first variable current;
and
wherein the folded cascode arrangement includes, within the second folded cascode branch:
a third tail generator transistor controlled by the first control voltage to source a seventh variable current to the second folded branch node, the seventh variable current being equal in magnitude to the fourth variable current;
and
a fourth tail generator transistor controlled by the second control voltage to sink an eighth variable current from the fourth folded branch node, the eighth variable current being equal in magnitude to the second variable current.

21 more elements

An operational transconductance amplifier (OTA), comprising:

a constant current source p-channel transistor having a source connected to a supply voltage node, a drain connected to a first node, and a gate coupled to a first control voltage;
a first input pair of transistors comprising:
a first input p-channel transistor having a source connected to the first node, a drain connected to a third folded branch node, and a drain coupled to a feedback voltage;
and
a second input p-channel transistor having a source connected to the first node, a drain connected to a fourth folded branch node, and a drain coupled to an input voltage;
a tail current source n-channel transistor having a drain connected to a second node, a source connected to ground, and a gate connected to a third node;
a second input pair of transistors comprising:
a first input n-channel transistor having a drain connected to a first folded branch node, a source connected to the second node, and a gate coupled to the feedback voltage;
and
a second input n-channel transistor having a drain connected to a second folded branch node, a source connected to the second node, and a gate coupled to the input voltage;
a first mirror n-channel transistor having a drain and a gate connected to the third node, and a source connected to ground;
a second mirror p-channel transistor having a source connected to the first node, a drain connected to the third node, and a gate connected to a fourth node;
a third mirror p-channel transistor having a source connected to the supply voltage node, and a drain and a gate connected to the fourth node;
a tail n-channel transistor having a drain connected to the fourth node, a source connected to ground, and a gate coupled to a second control voltage;
a bias stage comprising:
a first bias p-channel transistor having a source connected to the supply voltage node, a drain connected to a first bias node, and a gate coupled to the first control voltage;
a first bias n-channel transistor having a drain connected to the first bias node, a source connected to ground, and a gate coupled to the first bias node;
a second bias n-channel transistor having a drain connected to the first bias node, a source connected to ground, and a gate coupled to the second control voltage;
a second bias p-channel transistor having a source connected to the supply voltage node, and a drain and gate connected to a second bias node;
and
a third bias n-channel transistor having a drain connected to the second bias node, a source connected to ground, and a gate coupled to the third node;
a folded cascode arrangement comprising, within a first folded cascode branch:
a first tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to the first folded branch node, and a gate connected to the second bias node;
and
a first tail generator n-channel transistor having a drain connected to the third folded branch node, a source connected to ground, and a gate connected to the first bias node;
the folded cascode arrangement comprising, within a second folded cascode branch:
a second tail generator p-channel transistor having a source connected to the supply voltage node, a drain connected to the second folded branch node, and a gate connected to the first bias node;
a second tail generator n-channel transistor having a drain connected to the fourth folded branch node, a source connected to ground, and a gate connected to the first bias node;
and
a Monticelli cell coupled between the drain of the second tail generator p-channel transistor and the drain of the second tail generator n-channel transistor;
and
a class-AB output stage having inputs coupled across the Monticelli cell and an output connected to an output node.

29 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/535,046Filed 11 Dec 2023
Published: US 2025/0192740 A112 Jun 2025
Granted: 15 Sep 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03F 3/45219
Complementary long tailed pairs having parallel inputs and being supplied in parallel: folded cascode stages
H03F 3/211
With semiconductor devices only: using a combination of several amplifiers
H03F 2203/45288
Indexing scheme relating to differential amplifiers: differential amplifier with circuit arrangements to enhance the transconductance
H03F 2203/45541
Indexing scheme relating to differential amplifiers: the IC comprising dynamic biasing means, i.e. controlled by the input signal