Active balun amplifier

A low noise amplifier circuit for automatic gain control, the low noise amplifier circuit comprising:

• a plurality of active balun amplifiers, wherein each active balun amplifier of the plurality of active balun amplifiers comprises:
• a first plurality of metal oxide semiconductor (MOS) transistors arranged in series, the first plurality of MOS transistors comprising a first input transistor of a first conductivity type,
• a second input transistor of a second conductivity type, and
• at least two common-gate transistors arranged in series between the first input transistor and the second input transistor;
• a second plurality of MOS transistors arranged in series, the second plurality of MOS transistors comprising:
• a first common-source transistor of the first conductivity type,
• a second common-source transistor of the second conductivity type, and
• at least two cascode transistors arranged in series between the first common-source transistor and the second common-source transistor;
• and
• a coupling capacitor, wherein a first end of the coupling capacitor is coupled to a first coupling point located between the first input transistor and a first common-gate transistor and to a gate of the first common-source transistor, and wherein a second end of the coupling capacitor is coupled to a second coupling point located between the second input transistor and a second common-gate transistor and to a gate of the second common-source transistor.

A transceiver, comprising:

• a low noise amplifier circuit for automatic gain control, wherein the low noise amplifier circuit comprises:
• a plurality of active balun amplifiers, wherein each active balun amplifier of the plurality of active balun amplifiers comprises:
• a first plurality of metal oxide semiconductor (MOS) transistors arranged in series, the first plurality of MOS transistors comprising a first input transistor of a first conductivity type,
• a second input transistor of a second conductivity type, and
• at least two common-gate transistors arranged in series between the first input transistor and the second input transistor;
• a second plurality of MOS transistors arranged in series, the second plurality of MOS transistors comprising a first common-source transistor of the first conductivity type, a second common-source transistor of the second conductivity type, and at least two cascode transistors arranged in series between the first common-source transistor and the second common-source transistor;
• and
• a coupling capacitor, wherein a first end of the coupling capacitor is coupled to a first coupling point located between the first input transistor and a first common-gate transistor and to a gate of the first common-source transistor, and wherein a second end of the coupling capacitor is coupled to a second coupling point located between the second input transistor and a second common-gate transistor and to a gate of the second common-source transistor.