Gate driver circuit and process for reducing dead time duration upon switching
AssigneeMitsubishi Electric Corporation
InventorsJohan Le Lesle, Guillaume Lefevre
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AssigneeMitsubishi Electric Corporation
InventorsJohan Le Lesle, Guillaume Lefevre
Estimating the term…
Gate driver circuit, for a half bridge of a converter where a first switching device and a second switching device are controlled independently and in a complementary way comprising a first gate current mirroring circuit on a sink branch of a first gate driver buffer and a second gate current mirroring circuit on a sink branch of a second gate driver buffer to provide, in advance from pulse signals issued from the controller, a first early gate pullup command signal issuing from the first gate current mirroring circuit, for the second gate driver buffer under a turning off of a first switching device and a second early gate pullup command signal issuing from the second gate current mirroring circuit, for the first gate driver buffer from a turning off of a second switching device, in advance from gate pull up pulse signals issued from the controller.
A gate driver circuit, for a half bridge of a converter where a first switching device, having a first gate, and a second switching device, having a second gate, are controlled independently and in a complementary way respectively through a first gate driver buffer and a second gate driver buffer, and a controller providing gate pull up and gate pull down pulse signals to the first and second gate drivers buffers, characterized in that it comprises a first gate current mirroring circuit on a sink branch of said first gate driver buffer and a second gate current mirroring circuit on a sink branch of said second gate driver buffer to provide, in advance from said pulse signals issued from the controller, a first early gate pullup command signal issuing from the first gate current mirroring circuit, for the second gate driver buffer under a turning off of said first switching device and a second early gate pullup command signal issuing from the second gate current mirroring circuit, for the first gate driver buffer from a turning off of said second switching device, in advance from gate pull up pulse signals issued from the controller.
A process for reducing the dead time duration upon switching of switches in a half bridge of a converter comprising sensing of a gate current in a gate driver circuit during an on to off switching transition of a first switch of said half bridge using current mirror to provide a mirrored gate current signal, transferring said mirrored gate current signal through a galvanic insulation circuit, conditioning said mirrored gate current signal to create a gate pull-up command signal, combining said gate pull-up command signal with a gate command signal of a second switch of said half bridge in order to provide an advanced off to on transition of said second switch.
Dependencies are inferred from the claim text.