Semiconductor manufacturing apparatus

A semiconductor manufacturing apparatus, comprising:

• a chamber including an interior wall forming a space where plasma is generated, the interior wall including a lower interior wall where an electrostatic chuck is disposed, and an upper interior wall disposed higher than the lower interior wall, the electrostatic chuck configured to support a wafer thereon,
• the upper interior wall including an upper member, the upper member comprising:
• a base having a ring configuration, the base including a first surface facing inside of the ring configuration thereof, a second surface crossing the first surface, a third surface crossing the first surface, a first edge portion connecting the first surface and the second surface, and a second edge portion connecting the first surface and the third surface, the second edge portion being higher than the first edge portion;
• and
• a particle-resistant layer including a polycrystalline ceramic, the particle-resistant layer being formed by aerosol deposition, the particle-resistant layer including
• a first particle-resistant layer provided at the first edge portion,
• a second particle-resistant layer provided at the first surface, and
• a third particle-resistant layer provided at the second surface,
• wherein a particle resistance of the first particle-resistant layer is higher than a particle resistance of the second particle-resistant layer, and
• wherein a thickness of the first particle-resistant layer is thinner than a thickness of the second particle-resistant layer.